# US 2021/0242239 A1 · Semiconductor memory structure and device

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- Number: US 2021/0242239 A1
- Document ID: US20210242239A1
- Status: Published application
- Kind: A1
- Application number: 16/892,038
- Filed: 2020-06-03
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: YU-MING LIN; CHUN-CHIEH LU; BO-FENG YOUNG; HAN-JONG CHIA; CHENCHEN JACOB WANG; SAI-HOOI YEONG
- Web page: https://patentgrep.com/patent/US20210242239A1

## CPC

- G11C 16/24: Bit-line control circuits
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/2255: {Bit-line or column circuits}
- G11C 11/2257: {Word-line or row circuits}
- G11C 11/2259: {Cell access}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 51/10: characterised by the top-view layout
- H10B 51/30: characterised by the memory core region
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.

## Claims

### Claim 1

A semiconductor memory structure, comprising:
a semiconductor layer;
a conductive layer disposed over the semiconductor layer;
a gate penetrating through the conductive layer and the semiconductor layer; and
an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer,
wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.

### Claim 2 (depends on 1)

The semiconductor memory structure of claim 1, wherein the interposing layer comprises a dielectric structure.

### Claim 3 (depends on 1)

The semiconductor memory structure of claim 1, wherein the interposing layer comprises a ferroelectric layer.

### Claim 4 (depends on 1)

The semiconductor memory structure of claim 1, further comprising a source region and a drain region formed in the conductive layer.

### Claim 5 (depends on 1)

The semiconductor memory structure of claim 1, further comprising a substrate and an insulating layer disposed between the substrate and the semiconductor layer.

### Claim 6

A semiconductor memory structure, comprising:
a stack of alternating insulating layers, semiconductor layers and conductive layers;
a plurality of gates arranged in an array configuration of rows and columns, and penetrating through the stack; and
an interposing layer surrounding each of the gates,
wherein a pair of channel regions is formed in the semiconductor layers at two sides of each of the gates.

### Claim 7 (depends on 6)

The semiconductor memory structure of claim 6, wherein the gates are arranged in a staggered array configuration.

### Claim 8 (depends on 6)

The semiconductor memory structure of claim 6, wherein the interposing layer comprises a dielectric structure.

### Claim 9 (depends on 6)

The semiconductor memory structure of claim 6, wherein the interposing layer comprises a ferroelectric layer.

### Claim 10 (depends on 6)

The semiconductor memory structure of claim 6, further comprising a source region and a drain region formed in each of the conductive layers.

### Claim 11 (depends on 6)

The semiconductor memory structure of claim 6, wherein the stack further comprises an uppermost insulating layer.

### Claim 12

A semiconductor memory structure comprising a stack of alternating insulating layers, semiconductor layers and conductive layers, the stack comprising:
a memory array region comprising:
a plurality of gates arranged in an array configuration of rows and columns and penetrating through the stack;
an interposing layer surrounding each of the gates; and
a plurality of word line connectors disposed on the gates;
a plurality of first connection regions adjoined to the memory array region, extending along a column direction and configured in a staircase structure, each of the first connection regions comprising:
a plurality of stepped surfaces of the conductive layers; and
a plurality of bit line connectors disposed on the stepped surfaces of the conductive layers; and
a plurality of second connection regions spaced apart from the first connection regions, adjoined to the memory array region, extending along the column direction and configured in a staircase structure, each of the second connection regions comprising:
a plurality of stepped surfaces of the conductive layers; and
a plurality of source line connectors disposed on the stepped surfaces of the conductive layers.

### Claim 13 (depends on 12)

The semiconductor memory structure of claim 12, wherein the bit line connectors arranged along the column direction have different heights, and the source line connectors arranged along the column direction have different heights.

### Claim 14 (depends on 12)

The semiconductor memory structure of claim 12, wherein the gates are arranged in a staggered array configuration.

### Claim 15 (depends on 12)

The semiconductor memory structure of claim 12, wherein the first connection regions and the second connection regions are disposed at a same side of the memory array region.

### Claim 16 (depends on 12)

The semiconductor memory structure of claim 12, wherein the memory array region is disposed between the first connection regions and the second connection regions.

### Claim 17 (depends on 12)

The semiconductor memory structure of claim 12, wherein the gates arranged along the column direction are disposed between one of the first connection regions and an adjacent second connection region, between two adjacent first connection regions, or between two adjacent second connection regions.

### Claim 18 (depends on 12)

The semiconductor memory structure of claim 12, further comprising a plurality of isolation regions adjoined to the memory array region, extending along the column direction and configured in a staircase structure, wherein each of the isolation regions is disposed between one of the first connection regions and an adjacent second connection region, between two adjacent first connection regions, or between two adjacent second connection regions.

### Claim 19 (depends on 12)

The semiconductor memory structure of claim 12, wherein the word line connectors, the bit line connectors and the source line connectors are disposed over the memory array.

### Claim 20 (depends on 12)

The semiconductor memory structure of claim 12, wherein the word line connectors are disposed under the memory array, and the bit line connectors and the source line connectors are disposed over the memory array.