# US 2021/0242237 A1 · Three-dimensional semiconductor memory device

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- Number: US 2021/0242237 A1
- Document ID: US20210242237A1
- Status: Published application
- Kind: A1
- Application number: 17/216,867
- Filed: 2021-03-30
- Published: 2021-08-05
- Earliest claimed: 2018-06-21
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Geunwon LIM; SangJun HONG; Seokcheon BAEK
- Web page: https://patentgrep.com/patent/US20210242237A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/037: {comprising charge-trapping insulators}
- H10W 20/42: Vias, e.g. via plugs
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/40: characterised by the peripheral circuit region
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.

## Claims

### Claim 1

A three-dimensional semiconductor memory device comprising:
a bottom substrate;
a peripheral logic structure on the bottom substrate;
a top substrate including a first conductive pattern, a second conductive pattern, and a third conductive pattern sequentially stacked on the peripheral logic structure;
an electrode structure including gate electrodes stacked on the top substrate;
vertical holes passing through the electrode structure, the third conductive pattern and the second conductive pattern;
vertical semiconductor patterns in the vertical holes, respectively; and
a data storage pattern between each of the vertical semiconductor patterns and the electrode structure,
wherein bottom surfaces of the vertical holes are lower than a bottom surface of the first conductive pattern,
wherein the data storage pattern includes a tunnel insulation layer, a blocking layer, and a charge storage layer between the tunnel insulation layer and the blocking layer,
wherein a bottom surface of at least one of the tunnel insulation layer, the blocking layer, and the charge storage layer is lower than the bottom surface of the first conductive pattern,
wherein the second conductive pattern is connected to the vertical semiconductor patterns.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first conductive pattern includes tungsten, titanium, tantalum, and/or a conductive nitride thereof.

### Claim 3 (depends on 1)

The device of claim 1, wherein a lower surface of the second conductive pattern contacts an upper surface of the first conductive pattern.

### Claim 4 (depends on 1)

The device of claim 1, wherein the second conductive pattern comprises:
vertical portions extending along sidewalls of the vertical semiconductor patterns; and
a horizontal portion laterally extending from the vertical portions and below the electrode structure.

### Claim 5 (depends on 4)

The device of claim 4, wherein lower portions of the vertical portions of the second conductive pattern are connected to an upper portion of the first conductive pattern.

### Claim 6 (depends on 1)

The device of claim 1, wherein the electrode structure includes a plurality of electrode structures separated by a gap-fill insulation pattern, and
wherein the gap-fill insulation pattern passes through the first conductive pattern.

### Claim 7 (depends on 6)

The device of claim 6, further comprising:
a first wiring on the electrode structure;
a second wiring between the first conductive pattern and the bottom substrate; and
a through via passing through the gap-fill insulation pattern to connect the first wiring and the second wiring.

### Claim 8

A three-dimensional semiconductor memory device comprising:
a bottom substrate;
a peripheral logic structure on the bottom substrate;
a top substrate including a first conductive pattern, a second conductive pattern, and a third conductive pattern sequentially stacked on the peripheral logic structure;
an electrode structure including gate electrodes stacked on the top substrate;
vertical holes passing through the electrode structure, the third conductive pattern and the second conductive pattern;
vertical semiconductor patterns in the vertical holes, respectively; and
a data storage pattern between each of the vertical semiconductor patterns and the electrode structure,
wherein bottom surfaces of the vertical holes are lower than a bottom surface of the first conductive pattern,
wherein the data storage pattern includes a tunnel insulation layer, a blocking layer, and a charge storage layer between the tunnel insulation layer and the blocking layer,
wherein the second conductive pattern is connected to the vertical semiconductor patterns.

### Claim 9 (depends on 8)

The device of claim 8, wherein a bottom surface of at least one of the tunnel insulation layer, the blocking layer, and the charge storage layer is lower than the bottom surface of the first conductive pattern.

### Claim 10 (depends on 8)

The device of claim 8, wherein the first conductive pattern includes tungsten, titanium, tantalum, and/or a conductive nitride thereof.

### Claim 11 (depends on 8)

The device of claim 8, wherein a lower surface of the second conductive pattern contacts an upper surface of the first conductive pattern.

### Claim 12 (depends on 8)

The device of claim 8, wherein the second conductive pattern comprises:
vertical portions extending along sidewalls of the vertical semiconductor patterns; and
a horizontal portion laterally extending from the vertical portions and below the electrode structure.

### Claim 13 (depends on 12)

The device of claim 12, wherein lower portions of the vertical portions of the second conductive pattern are connected to an upper portion of the first conductive pattern.

### Claim 14 (depends on 8)

The device of claim 8, wherein the electrode structure includes a plurality of electrode structures separated by a gap-fill insulation pattern, and
wherein the gap-fill insulation pattern passes through the first conductive pattern.

### Claim 15 (depends on 14)

The device of claim 14, further comprising:
a first wiring on the electrode structure;
a second wiring between the first conductive pattern and the bottom substrate; and
a through via passing through the gap-fill insulation pattern to connect the first wiring and the second wiring.

### Claim 16

A three-dimensional semiconductor memory device comprising:
a bottom substrate;
a peripheral logic structure on the bottom substrate;
a top substrate including a first conductive pattern, a second conductive pattern, and a third conductive pattern sequentially stacked on the peripheral logic structure;
an electrode structure including gate electrodes stacked on the top substrate;
vertical holes passing through the electrode structure, the third conductive pattern and the second conductive pattern;
vertical semiconductor patterns in the vertical holes, respectively; and
a data storage pattern between each of the vertical semiconductor patterns and the electrode structure,
wherein bottom surfaces of the vertical holes are lower than a bottom surface of the first conductive pattern,
wherein the data storage pattern includes a tunnel insulation layer, a blocking layer, and a charge storage layer between the tunnel insulation layer and the blocking layer.

### Claim 17 (depends on 16)

The device of claim 16, wherein the second conductive pattern is connected to the vertical semiconductor patterns.

### Claim 18 (depends on 16)

The device of claim 16, wherein a bottom surface of at least one of the tunnel insulation layer, the blocking layer, and the charge storage layer is lower than the bottom surface of the first conductive pattern.

### Claim 19 (depends on 16)

The device of claim 16, wherein the first conductive pattern including tungsten, titanium, tantalum, and/or a conductive nitride thereof.

### Claim 20 (depends on 16)

The device of claim 16, wherein a lower surface of the second conductive pattern contacts an upper surface of the first conductive pattern.