# US 2021/0242236 A1 · Three-dimensional semiconductor memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242236 A1 - Document ID: US20210242236A1 - Status: Published application - Kind: A1 - Application number: 17/036,997 - Filed: 2020-09-29 - Published: 2021-08-05 - Earliest claimed: 2020-02-05 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Seungjun Shin; Siwan Kim; Bonghyun Choi - Web page: https://patentgrep.com/patent/US20210242236A1 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/40: characterised by the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 20/42: Vias, e.g. via plugs - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other. ## Claims ### Claim 1 A three-dimensional (3D) semiconductor memory device comprising: a semiconductor substrate; electrode structures comprising a plurality of electrodes stacked on the semiconductor substrate, the electrode structures extending in a first direction and being spaced apart from each other by separation regions in a second direction perpendicular to the first direction; ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein the separation regions comprise a first end portion on a level of the ground select gate electrodes; and at least one ground select gate cutting region that overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other. ### Claim 2 (depends on 1) The device of claim 1, wherein the semiconductor substrate comprises a cell array region and a connection region, the electrode structures extend from the cell array region to the connection region in the first direction, and the at least one ground select gate cutting region is in the cell array region or the connection region. ### Claim 3 (depends on 1) The device of claim 1, wherein the separation regions further comprise a second end portion spaced apart from the first end portion and opposite to the first end portion, and wherein the at least one ground select gate cutting region overlaps both the first end portion and the second end portion of the separation regions. ### Claim 4 (depends on 1) The device of claim 1, wherein a length of the at least one ground select gate cutting region in the second direction is greater than a length of the separation regions in the second direction. ### Claim 5 (depends on 1) The device of claim 1, wherein a length of the at least one ground select gate cutting region in the second direction is less than a length of the separation regions in the second direction. ### Claim 6 (depends on 1) The device of claim 1, wherein the separation regions comprise a first isolation region comprising the first end portion and a second isolation region comprising a second end portion spaced apart from the first isolation region in the first direction, and wherein the at least one ground select gate cutting region overlaps the first end portion of the first isolation region and the second end portion of the second isolation region in a third direction that is perpendicular to the first direction and the second direction. ### Claim 7 (depends on 1) The device of claim 1, wherein a first length of the at least one ground select gate cutting region in the first direction is less than a second length thereof in the second direction. ### Claim 8 (depends on 1) The device of claim 1, wherein a first length of the at least one ground select gate cutting region in the first direction is greater than a second length thereof in the second direction. ### Claim 9 (depends on 1) The device of claim 1, wherein the at least one ground select gate cutting region is line-shaped, I-shaped, or line-shaped with an inner via opening. ### Claim 10 (depends on 1) The device of claim 1, wherein the separation regions comprise an electrode isolation region or a gate isolation region. ### Claim 11 A three-dimensional (3D) semiconductor memory device comprising: a peripheral logic structure on a semiconductor substrate; a horizontal semiconductor layer on the peripheral logic structure, the horizontal semiconductor layer comprising a cell array region and a connection region electrically connected to the cell array region; electrode structures comprising a plurality of electrodes stacked on the horizontal semiconductor layer in the cell array region and the connection region, the electrode structures extending in a first direction and being spaced apart from each other by separation regions in a second direction perpendicular to the first direction; at least one contact region comprising a through wiring structure electrically connecting the electrode structures to the peripheral logic structure in the connection region; and ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures in the cell array region and the connection region, wherein the separation regions comprise a first end portion on a level of the ground select gate electrodes, and wherein at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other. ### Claim 12 (depends on 11) The device of claim 11, wherein the at least one ground select gate cutting region overlaps the at least one contact region on the level of the ground select gate electrodes. ### Claim 13 (depends on 11) The device of claim 11, wherein the at least one contact region comprises a plurality of contact regions spaced apart from each other in the first direction, and wherein the at least one ground select gate cutting region is between the plurality of contact regions. ### Claim 14 (depends on 11) The device of claim 11, wherein the separation regions comprise first and second portions that are spaced apart from the at least one contact region in the second direction, and wherein the first and second portions of the separation regions are in parallel with each other in a straight line shape in the first direction. ### Claim 15 (depends on 11) The device of claim 11, wherein, on the level of the ground select gate electrodes, a profile of one side surface of the ground select gate electrodes adjacent to the at least one contact region and the at least one ground select gate cutting region is curve-shaped. ### Claim 16 A three-dimensional (3D) semiconductor memory device comprising: a peripheral logic structure on a semiconductor substrate; a horizontal semiconductor layer on the peripheral logic structure, the horizontal semiconductor layer comprising a cell array region and a connection region electrically connected to the cell array region; electrode structures comprising a plurality of electrodes stacked on the horizontal semiconductor layer in the cell array region and the connection region, the electrode structures each extending in a first direction and being spaced apart from each other by at least one separation region in a second direction perpendicular to the first direction; at least one contact region comprising a through wiring structure electrically connecting the electrode structures to the peripheral logic structure in the connection region; and ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures in the cell array region and the connection region, wherein the at least one separation region comprises a first end portion on a level of the ground select gate electrodes, and wherein at least one ground select gate cutting region overlaps the first end portion of the at least one separation region and electrically isolates the ground select gate electrodes from each other. ### Claim 17 (depends on 16) The device of claim 16, wherein the cell array region has a first length in the second direction, and the connection region has a second length in the second direction, the second length being greater than the first length. ### Claim 18 (depends on 16) The device of claim 16, wherein the cell array region comprises a plurality of memory blocks in the second direction, wherein the memory blocks are divided into a first memory block group and a second memory block group, wherein the connection region comprises a first connection region and a second connection region, and wherein the first memory block group and the second memory block group are electrically connected to the first connection region and the second connection region, respectively, in the first direction on a first side and a second side of the cell array region, respectively. ### Claim 19 (depends on 16) The device of claim 16, wherein the connection region comprises a stepped region of the plurality of electrodes, and wherein the at least one ground select gate cutting region is in the cell array region or is in the connection region. ### Claim 20 (depends on 16) The device of claim 16, wherein the at least one ground select gate cutting region overlaps a second end portion of the at least one separation region or overlaps a portion of the through wiring structure.