# US 2021/0242235 A1 · Semiconductor memory devices having stacked structures therein that support high integration > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242235 A1 - Document ID: US20210242235A1 - Status: Published application - Kind: A1 - Application number: 16/985,024 - Filed: 2020-08-04 - Published: 2021-08-05 - Earliest claimed: 2020-02-04 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sangjae Lee; Jaehyung Kim; Dongseog Eun - Web page: https://patentgrep.com/patent/US20210242235A1 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate having a lower stack structure thereon, said lower stack structure comprising an alternating vertical arrangement of a plurality of lower insulating layers and a plurality of lower electrode layers, and said plurality of lower electrode layers including at least first and second lower electrode layers; an upper stack structure on the lower stack structure, said upper stack structure comprising an alternating vertical arrangement of a plurality of upper insulating layers and a plurality of upper electrode layers, and said plurality of upper electrode layers including at least first and second upper electrode layers; and a channel structure extending at least partially through the upper stack structure and at least partially through the lower stack structure; wherein the first lower electrode layer and/or the first upper electrode layer is thicker than the second lower electrode layer; wherein at least one of the plurality of lower insulating layers and at least one of the plurality of upper insulating layers are disposed between the first lower electrode layer and the first upper electrode layer; wherein, among the plurality of lower electrode layers, the first lower electrode layer is disposed nearest an interface between the lower stack structure and the upper stack structure; and wherein, among the plurality of upper electrode layers, the first upper electrode layer is disposed nearest the interface. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first lower electrode layer is thicker than the second lower electrode layer; wherein the second lower electrode layer extends adjacent a center of the lower stack structure; and wherein the second upper electrode layer extends adjacent a center of the upper stack structure. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the first upper electrode layer and the second upper electrode layer have substantially the same thicknesses. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first upper electrode layer is thicker than the second upper electrode layer. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the second upper electrode layer and the second lower electrode layer have substantially the same thicknesses. ### Claim 6 (depends on 4) The semiconductor device of claim 4, wherein the first and second lower electrode layers have substantially the same thicknesses. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the plurality of lower insulating layers includes a first lower insulating layer extending between the first lower electrode layer and the first upper electrode layer. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein the first lower insulating layer is thicker than a second lower insulating layer, which extends between the first lower insulating layer and the substrate. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein a third one of the plurality of upper electrode layers extends farthest from the interface relative to all other ones of the plurality of upper electrode layers, and is thicker than the second upper electrode layer. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein a fourth one of the plurality of upper electrode layers extends between the first and second upper electrode layers and is thicker than the second upper electrode layer. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein at least one of the plurality of upper insulating layers extends between the first upper electrode layer and the lower stack structure. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein a third one of the plurality of lower electrode layers extends between the second lower electrode layer and the substrate and is thicker than the second lower electrode layer. ### Claim 13 (depends on 1) The semiconductor device of claim 1, further comprising: a horizontal conductive layer extending between the substrate and the lower stack structure; a support extending between the horizontal conductive layer and the lower stack structure; and a connecting conductive layer extending between the horizontal conductive layer and the support; wherein the channel structure extends through the upper stack structure, the lower stack structure and the support, and into an inside of the horizontal conductive layer. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the channel structure comprises a channel layer, a blocking layer disposed outside the channel layer, a charge storage layer disposed between the channel layer and the blocking layer, and a tunnel insulating layer disposed between the channel layer and the charge storage layer; and wherein the connecting conductive layer contacts the channel layer while extending through the blocking layer, the charge storage layer and the tunnel insulating layer. ### Claim 15 (depends on 13) The semiconductor device of claim 13, further comprising a plurality of transistors extending between the substrate and the horizontal conductive layer. ### Claim 16 A semiconductor memory device, comprising: a horizontal conductive layer on a substrate; a lower stack structure on the horizontal conductive layer, said lower stack structure comprising an alternating vertical arrangement of a plurality of lower insulating layers and a plurality of lower electrode layers; an upper stack structure disposed on the lower stack structure, said upper stack structure comprising an alternating vertical arrangement of a plurality of upper insulating layers and a plurality of upper electrode layers; a channel structure extending through the upper stack structure and the lower stack structure and into an inside of the horizontal conductive layer; and a bit line on the upper stack structure, which is electrically connected the channel structure; wherein a first one of the lower electrode layers disposed nearest an interface between the lower stack structure and the upper stack structure relative to all other ones of the lower electrode layer is thicker than a second one of the lower electrode layers, which extends between the first lower electrode layer and the substrate; and wherein at least one of the plurality of lower insulating layers and the plurality of upper insulating layers directly contacts the interface. ### Claim 17 (depends on 16) The semiconductor memory device of claim 16, wherein a first lower insulating layer extending nearest the interface among the plurality of lower insulating layers is thicker than a second lower insulating layer extending adjacent a center of the lower stack structure; and wherein the first lower insulating layer directly contacts the interface. ### Claim 18 A semiconductor device, comprising: a horizontal conductive layer disposed on a substrate; a lower stack structure disposed on the horizontal conductive layer, the lower stack structure comprising a plurality of lower insulating layers and a plurality of lower electrode layers which are alternately repeatedly stacked; an upper stack structure disposed on the lower stack structure, the upper stack structure comprising a plurality of upper insulating layers and a plurality of upper electrode layers which are alternately repeatedly stacked; a channel structure extending through the upper stack structure and the lower stack structure and into an inside of the horizontal conductive layer; and a bit line disposed on the upper stack structure and electrically connected to the channel structure; wherein a first upper electrode layer disposed nearest an interface between the lower stack structure and the upper stack structure relative to all other ones of the plurality of upper electrode layers is thicker than a second upper electrode layer extending adjacent a center of the upper stack structure; and wherein at least one of the plurality of lower insulating layers and the plurality of upper insulating layers directly contacts the interface. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein a first lower electrode layer extending nearest the interface relative to all other ones of the plurality of lower electrode layers is thicker than a second lower electrode layer extending adjacent a center of the lower stack structure. ### Claim 20 (depends on 18) The semiconductor device of claim 18, wherein a first lower electrode layer extending nearest the interface relative to all other ones of the plurality of lower electrode layers has a thickness substantially equal to a thickness of a second lower electrode layer extending adjacent a center of the lower stack structure.