# US 2021/0242234 A1 · Semiconductor device and manufacturing method of the semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242234 A1 - Document ID: US20210242234A1 - Status: Published application - Kind: A1 - Application number: 16/933,440 - Filed: 2020-07-20 - Published: 2021-08-05 - Earliest claimed: 2020-01-30 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Nam Jae LEE - Web page: https://patentgrep.com/patent/US20210242234A1 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/10: characterised by the top-view layout - H10B 43/35: with cell select transistors, e.g. NAND - H10B: ELECTRONIC MEMORY DEVICES ## Abstract There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure; a source structure; a channel structure penetrating the stack structure, the channel structure being connected to the source structure; and a first memory layer interposed between the channel structure and the stack structure. The source structure includes a first protrusion part protruding between the first memory layer and the channel structure. ## Claims ### Claim 1 A semiconductor device comprising: a stack structure; a source structure including a first protrusion part protruding toward the stack structure; a channel structure penetrating the stack structure, the channel structure being connected to the source structure; a first tunnel insulating layer interposed between the channel structure and the stack structure; a first data storage layer interposed between the first tunnel insulating layer and the stack structure; and a first blocking layer interposed between the first data storage layer and the stack structure, wherein the first protrusion part is in contact with a bottom surface of the first tunnel insulating layer, a bottom surface of the first data storage layer, and a sidewall of the first blocking layer. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a surface of the first protrusion part, which is in contact with the first tunnel insulating layer, the first data storage layer, and the first blocking layer, has a step shape. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the bottom surface of the first tunnel insulating layer, the bottom surface of the first data storage layer, and a bottom surface of the first blocking layer are located at different levels. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the bottom surface of the first blocking layer is located at a level lower than a level of the bottom surface of the first tunnel insulating layer and a level of the bottom surface of the first data storage layer. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the bottom surface of the first data storage layer is located at a level lower than that of the bottom surface of the first tunnel insulating layer. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the bottom surface of the first data storage layer is located at substantially the same level as the bottom surface of the first tunnel insulating layer. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the first blocking layer includes a first blocking part surrounding the first data storage layer and a second blocking part surrounding the first protrusion part, wherein a width of the second blocking part is smaller than that of the first blocking part. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein a top surface of the source structure is in contact with the bottom surface of the first blocking layer. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the first protrusion part includes a first part in contact with the bottom surface of the first tunnel insulating layer and located between the first data storage layer and the channel structure, and a second part in contact with the bottom surface of the first data storage layer and the a bottom surface of the first part and located between the first blocking layer and the channel structure. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the second part has a greater width than the first part. ### Claim 11 (depends on 9) The semiconductor device of claim 9, wherein a width of the first part is substantially the same as a width of the first tunnel insulating layer. ### Claim 12 (depends on 9) The semiconductor device of claim 9, wherein a width of the first tunnel insulating layer is less than a width of the first blocking layer. ### Claim 13 A semiconductor device comprising: a source structure; a stack structure; a channel structure penetrating the stack structure, the channel structure being connected to the source structure; and a first memory layer interposed between the channel structure and the stack structure, wherein the source structure includes a first protrusion part protruding between the first memory layer and the channel structure, wherein the first protrusion part has a stepped structure. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the source structure includes: a first source layer; an etch stop layer on the first source layer; and a second source layer on the etch stop layer. ### Claim 15 (depends on 14) The semiconductor device of claim 14, further comprising a second memory layer interposed between the channel structure and the first source layer. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein the second source layer includes a second protrusion part protruding between the second memory layer and the channel structure, wherein the second protrusion part has a stepped structure. ### Claim 17 (depends on 13) The semiconductor device of claim 13, wherein the first protrusion part protrudes from a top surface of the source structure, wherein the stack structure includes an insulating pattern and a conductive pattern, wherein the top surface of the source structure is in contact with a bottom surface of the insulating pattern. ### Claim 18 (depends on 13) The semiconductor device of claim 13, wherein the first memory layer includes a first tunnel insulating layer surrounding the channel structure and a first data storage layer surrounding the first tunnel insulating layer, wherein the first tunnel insulating layer includes oxide including nitrogen, and the first data storage layer includes a nitride. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein the first memory layer further includes a first blocking layer surrounding the first data storage layer, wherein a concentration of nitrogen of the first tunnel insulating layer is higher than that of nitrogen of the first blocking layer. ### Claim 20 (depends on 13) The semiconductor device of claim 13, wherein the first memory layer includes a first tunnel insulating layer, a first data storage layer surrounding the first tunnel insulating layer, and a first blocking layer surrounding the first data storage layer, wherein a bottom surface of the first tunnel insulating layer, a bottom surface of the first data storage layer, and a bottom surface of the first blocking layer are located at different levels.