# US 2021/0242233 A1 · Three-dimensional memory devices and methods for forming the same

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- Number: US 2021/0242233 A1
- Document ID: US20210242233A1
- Status: Published application
- Kind: A1
- Application number: 17/234,774
- Filed: 2021-04-19
- Published: 2021-08-05
- Earliest claimed: 2019-09-29
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Hongbin Zhu
- Web page: https://patentgrep.com/patent/US20210242233A1

## CPC

- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/697: {having trapping at multiple separated sites, e.g. multi-particles trapping sites}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming a 3D memory device is disclosed. A gate electrode having an inverted “T” shape is formed above a substrate. A continuous blocking layer is formed on the gate electrode. A continuous charge trapping layer is formed on the blocking layer. A first thickness of a first part of the charge trapping layer extending laterally is greater than a second thickness of a second part of the charge trapping layer extending vertically. The second part of the charge trapping layer extending vertically is removed to form a plurality of discrete charge trapping layers disposed at different levels on the blocking layer from the first part of the charge trapping layer extending laterally. A continuous tunneling layer is formed on the discrete charge trapping layers. A continuous channel layer is formed on the tunneling layer.

## Claims

### Claim 1

A method for forming a three-dimensional (3D) memory device, comprising:
forming a gate electrode having an inverted “T” shape above a substrate;
forming a continuous blocking layer on the gate electrode;
forming a continuous charge trapping layer on the blocking layer, wherein a first thickness of a first part of the charge trapping layer extending laterally is greater than a second thickness of a second part of the charge trapping layer extending vertically;
removing the second part of the charge trapping layer extending vertically to form a plurality of discrete charge trapping layers disposed at different levels on the blocking layer from the first part of the charge trapping layer extending laterally;
forming a continuous tunneling layer on the discrete charge trapping layers; and
forming a continuous channel layer on the tunneling layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the gate electrode comprises:
depositing a gate electrode layer above the substrate; and
patterning the gate electrode layer to have the inverted “T” shape.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the gate electrode comprises:
depositing a first gate electrode layer above the substrate; and
depositing a second gate electrode layer on the first gate electrode layer, wherein a lateral dimension of the first gate electrode layer is greater than a lateral dimension of the second gate electrode layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the continuous charge trapping layer comprises depositing the charge trapping layer on the blocking layer using chemical vapor deposition (CVD).

### Claim 5 (depends on 4)

The method of claim 4, wherein the CVD comprises atomic layer deposition (ALD).

### Claim 6 (depends on 1)

The method of claim 1, wherein removing the second part of the charge trapping layer comprises etching the charge trapping layer using wet etching until the second part of the charge trapping layer extending vertically is removed.

### Claim 7 (depends on 1)

The method of claim 1, wherein a first thickness of a first part of the channel layer extending laterally is greater than a second thickness of a second part of channel layer extending vertically.

### Claim 8 (depends on 7)

The method of claim 7, further comprising removing the second part of the channel layer extending vertically to form a plurality of discrete channel layers disposed at different levels on the tunneling layer, wherein each of the channel layers corresponds to a respective one of the charge trapping layers.

### Claim 9 (depends on 8)

The method of claim 8, wherein forming the continuous channel layer comprises depositing the channel layer on the tunneling layer using CVD.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the continuous channel layer comprises depositing the channel layer on the tunneling layer using ALD.

### Claim 11 (depends on 8)

The method of claim 8, wherein removing the second part of the channel layer comprises etching the channel layer using wet etching until the second part of the channel layer extending vertically is removed.