# US 2021/0242231 A1 · Semiconductor memory device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242231 A1 - Document ID: US20210242231A1 - Status: Published application - Kind: A1 - Application number: 16/934,641 - Filed: 2020-07-21 - Published: 2021-08-05 - Earliest claimed: 2020-01-30 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jae Taek KIM; Hye Yeong JUNG - Web page: https://patentgrep.com/patent/US20210242231A1 ## CPC - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B 63/845: {the switching components being connected to a common vertical conductor} - H10B 41/10: characterised by the top-view layout - H10B 41/40: characterised by the peripheral circuit region - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/40: characterised by the peripheral circuit region - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side o surface and a step top surface. The peripheral contact structure is in contact with the step side surface. ## Claims ### Claim 1 A semiconductor memory device comprising: a peripheral transistor; a first insulating layer covering the peripheral transistor; a source layer on the first insulating layer; a stack structure on the source layer; and a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor, wherein the stack structure includes a stepped structure including a step side surface and a step top surface, and wherein the peripheral contact structure is in contact with the step side surface. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the peripheral contact structure includes: a peripheral contact electrically connected to the peripheral transistor; and a peripheral insulating layer surrounding the peripheral contact. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, further comprising a word line contact in contact with the step top surface. ### Claim 4 The semiconductor memory device of claim , further comprising a peripheral line electrically connecting the word line contact and the peripheral contact structure. ### Claim 5 (depends on 4) The semiconductor memory device of claim 4, wherein the peripheral line includes a first part extending in a first direction and a second part extending in a second direction intersecting with the first direction. ### Claim 6 (depends on 1) The semiconductor memory device of claim 1, further comprising a dummy contact structure penetrating the stack structure and the source layer. ### Claim 7 (depends on 6) The semiconductor memory device of claim 6, wherein the dummy contact structure includes: a dummy contact penetrating the stack structure and the source layer; and a dummy insulating layer surrounding the dummy contact. ### Claim 8 (depends on 6) The semiconductor memory device of claim 6, wherein the dummy contact structure is in contact with the step side surface. ### Claim 9 (depends on 1) The semiconductor memory device of claim 1, wherein the step top surface includes two step top surfaces connected to each other by the step side surfaces, wherein the peripheral contact structure penetrates both the two step top surfaces. ### Claim 10 A semiconductor memory device comprising: a peripheral transistor; a first insulating layer covering the peripheral transistor; a source layer on the first insulating layer; a stack structure on the source layer; and a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor, wherein the stack structure includes alternately stacked insulating patterns and conductive patterns, wherein the peripheral contact structure is in contact with the conductive patterns, and wherein a level of an uppermost portion of the peripheral contact structure is higher than a level of an uppermost conductive pattern among the conductive patterns. ### Claim 11 (depends on 10) The semiconductor memory device of claim 10, wherein the peripheral contact structure penetrates a side end portion of one of the conductive patterns. ### Claim 12 (depends on 10) The semiconductor memory device of claim 10, further comprising dummy contact structures penetrating the stack structure and the source layer. ### Claim 13 (depends on 12) The semiconductor memory device of claim 12, wherein the peripheral contact structure is disposed between the dummy contact structures. ### Claim 14 (depends on 12) The semiconductor memory device of claim 12, wherein the dummy contact structures include first dummy contact structures penetrating side end portions of the conductive patterns. ### Claim 15 (depends on 12) The semiconductor memory device of claim 12, further comprising a source contact connected to the source layer and a source insulating layer disposed between the source contact and the stack structure, wherein some of the dummy contact structures are in contact with the source insulating layer. ### Claim 16 (depends on 11) The semiconductor memory device of claim 11, wherein the dummy contact structures are electrically floated.