# US 2021/0242230 A1 · Charge trap memory devices

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- Number: US 2021/0242230 A1
- Document ID: US20210242230A1
- Status: Published application
- Kind: A1
- Application number: 16/781,527
- Filed: 2020-02-04
- Published: 2021-08-05
- Earliest claimed: 2020-02-04
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: Globalfoundries U.S. Inc.
- Inventors: Faraz KHAN; Dan MOY; Norman W. ROBSON; Robert KATZ; Darren L. ANAND; Toshiaki KIRIHATA
- Web page: https://patentgrep.com/patent/US20210242230A1

## CPC

- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10B 43/30: characterised by the memory core region
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/24: Bit-line control circuits
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/691: {having more than two programming levels}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

## Claims

### Claim 1

A semiconductor memory, comprising:
a charge trap transistor comprising a gate structure, a source region and a drain region; and
a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

### Claim 2 (depends on 1)

The semiconductor memory of claim 1, wherein the charge trap transistor further comprises a substrate, wherein the source region is an emitter, the drain region is a collector and the substrate is a base of a bipolar junction transistor (BJT).

### Claim 3 (depends on 2)

The semiconductor memory of claim 2, wherein the substrate comprises a p-doped substrate and a bulk p-substrate, the p-doped substrate is isolated from the bulk p-substrate for other devices.

### Claim 4 (depends on 2)

The semiconductor memory of claim 2, wherein the source region and the drain region are n-doped and the substrate is p-doped to form an n-p-n junction transistor.

### Claim 5 (depends on 2)

The semiconductor memory of claim 2, wherein the self-heating circuit selectively applies voltages to the gate structure to assist in the programming operation of the charge trap transistor.

### Claim 6 (depends on 2)

The semiconductor memory of claim 2, wherein the source region and the drain region are p-doped and the substrate is n-doped to form a p-n-p junction transistor.

### Claim 7 (depends on 2)

The semiconductor memory of claim 2, further comprising a substrate SUB line connected to the substrate, a word line (WL) connected to the gate structure, a bitline (BL) connected to the source region and a programming-line (PL) connected to the drain region, wherein the self-heating circuit comprises a plurality of transistors which selectively apply voltages to the SUB line, the WL, the BL and the PL.

### Claim 8 (depends on 1)

The semiconductor memory of claim 1, wherein in the erase operation, the self-heating circuit alternates the drain region between a first voltage and a second voltage.

### Claim 9 (depends on 8)

The semiconductor memory of claim 8, wherein the first voltage is high and the second voltage is low.

### Claim 10 (depends on 1)

The semiconductor memory of claim 1, wherein a channel region under the gate structure is self-heated by n-p-n current flowing from the drain region to the source region or vice versa.

### Claim 11 (depends on 10)

The semiconductor memory of claim 10, wherein during the erase operation, the source region is an emitter node and the drain region is a collector node of the charge trap transistor which de-traps electrons in a gate dielectric of the charge trap transistor.

### Claim 12

A semiconductor memory, comprising:
a charge trap transistor comprising a plurality of source regions and a drain region and a plurality of doped wells; and
a self-heating circuit is configured to selectively apply a bias in a first direction and a second, reverse direction to the source regions and the drain region to assist in an erase operation or a program operation of the charge trap transistor.

### Claim 13 (depends on 12)

The semiconductor memory of claim 12, wherein in the erase operation, the self-heating circuit is configured to reverse the drain region to a low voltage.

### Claim 14 (depends on 12)

The semiconductor memory of claim 12, wherein, in the erase operation, the self-heating circuit is configured to reverse the source region to a high voltage.

### Claim 15 (depends on 12)

The semiconductor memory of claim 12, wherein the self-heating circuit is configured to place the charge trap transistor in an OFF mode by raising the source to a high voltage while keeping the drain at a low voltage.

### Claim 16 (depends on 12)

The semiconductor memory of claim 12, wherein the self-heating circuit is configured to skew a charge distribution to the source region by reversing the direction of the bias.

### Claim 17

A semiconductor memory cell, comprising:
a Metal-Oxide-Semiconductor Filed-Effect Transistor (MOSFET) comprising a substrate, a gate structure, a high-k dielectric material under the gate structure, a source region and a drain region; and
a self-heating circuit is configured to apply a bias to the substrate, the high-k dielectric metal gate structure, the source region and the drain region,
wherein the high-k dielectric of the high-k dielectric metal gate structure releases a trapped charge when a bias direction applied to the MOSFET is alternated between the source region and the drain region.

### Claim 18 (depends on 17)

The semiconductor memory of claim 17, wherein the self-heating circuit alternates the drain region between a first voltage and a second voltage.

### Claim 19 (depends on 17)

The semiconductor memory of claim 17, wherein the self-heating circuit further generates an electric field from the bias, and the self-heating circuit is further is configured to alternate a direction of the electric field between the source region and the drain region.

### Claim 20 (depends on 17)

The semiconductor memory of claim 17, further comprising a triple well which isolates the p-doped substrate for biasing.