# US 2021/0242228 A1 · Dummy vertical structures for etching in 3d nand memory and other circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242228 A1 - Document ID: US20210242228A1 - Status: Published application - Kind: A1 - Application number: 16/782,953 - Filed: 2020-02-05 - Published: 2021-08-05 - Earliest claimed: 2020-02-05 - Assignees: Macronix International Co., Ltd. - Applicants: Macronix International Co., Ltd. - Inventors: Chih-Wei HU; Teng-Hao YEH; Yu-Wei JIANG - Web page: https://patentgrep.com/patent/US20210242228A1 ## CPC - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory device comprises a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad. An array of vertical pillars extends through the stack of patterned conductor layers, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers. The array has an array boundary proximal to the pad. A first set of isolation blocks extends through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad. A second set of isolation blocks inside the array boundary extends through the plurality of patterned conductor layers isolating the other strips from the pad. ## Claims ### Claim 1 A memory device, comprising: a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad; an array of vertical pillars extending through the stack of patterned conductor layers wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers, the array having an array boundary proximal to the pad; a first set of isolation blocks extending through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad; and a second set of isolation blocks inside the array boundary and extending through the plurality of patterned conductor layers isolating the other strips from the pad. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the second set of isolation blocks include isolation blocks connecting a pair of adjacent isolation blocks in the first set of isolation blocks. ### Claim 3 (depends on 1) The memory device of claim 1, wherein some of the vertical pillars between the pad and the other strips isolated from the pad are penetrated by the isolation blocks in the second set of isolation blocks inside the array boundary. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the array extends into the pad beyond an end of isolation blocks in the first set of isolation blocks by one or more vertical pillars. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the array of vertical pillars includes a plurality of vertical pillars used for memory cells in the strips continuous with the pad, and vertical pillars not used for memory cells disposed between the pad and the plurality of vertical pillars used for memory cells, comprising: a set of bit lines coupled to the plurality of vertical pillars used for memory cells in the strips continuous with the pad. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the conductive strips extend in a first direction, the vertical pillars used for memory cells and the vertical pillars not used for memory cells have a common pitch and a common width in the first direction. ### Claim 7 (depends on 5) The memory device of claim 5, wherein the conductive strips extend in a first direction, the vertical pillars not used for memory cells have a different width in the first direction than the vertical pillars used for memory cells. ### Claim 8 (depends on 1) The memory device of claim 1, comprising: a second pad, wherein the strips continuous with the first-mentioned pad are separated from the second pad at ends proximal to the second pad, and strips continuous with the second pad are separated from the first-mentioned pad at ends proximal to the first-mentioned pad. ### Claim 9 (depends on 1) The memory device of claim 1, comprising: a block of vertical pillars inside the array boundary; a third pad disposed opposite the first-mentioned pad in a second direction orthogonal to a first direction along which the conductive strips extend; first and second boundary rows of vertical pillars extending in the first direction through the stack of patterned conductor layers, the first and second boundary rows being disposed adjacent and spanning the first-mentioned pad and the block of vertical pillars, the vertical pillars in the first and second boundary rows not used for memory cells; and a block isolation structure extending through the stack of patterned conductor layers separating the first-mentioned pad from the third pad, the vertical pillars in the first and second boundary rows in contact with sides of the block isolation structure. ### Claim 10 (depends on 9) The memory device of claim 9, comprising: a second block of vertical pillars disposed opposite the first-mentioned block of vertical pillars in the second direction, the block isolation structure separating the first-mentioned block of vertical pillars from the second block of vertical pillars. ### Claim 11 A method for manufacturing a memory device, comprising: forming an array of holes through a stack of patterned conductor layers separated by insulating layers; forming an array of vertical pillars extending through the stack of patterned conductor layers in the holes in the array of holes; etching a first set of slits and a second set of slits through the stack of patterned conductor layers using a single mask, the first set of slits disposed across the holes in respective rows of holes, the second set of slits including slits connecting adjacent slits in the first set of slits at ends, thereby forming conductive strips including strips continuous with a pad and other strips isolated from the pad, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers, the array of vertical pillars having an array boundary proximal to the pad; forming a first set of isolation blocks in the first set of slits through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad; and forming a second set of isolation blocks in the second set of slits inside the array boundary and extending through the plurality of patterned conductor layers isolating the other strips from the pad. ### Claim 12 (depends on 11) The method of claim 11, wherein the second set of isolation blocks include isolation blocks connecting a pair of adjacent isolation blocks in the first set of isolation blocks. ### Claim 13 (depends on 11) The method of claim 11, wherein some of the vertical pillars between the pad and the other strips isolated from the pad are penetrated by the isolation blocks in the second set of isolation blocks inside the array boundary. ### Claim 14 (depends on 11) The method of claim 11, wherein the array extends into the pad beyond an end of isolation blocks in the first set of isolation blocks by one or more vertical pillars. ### Claim 15 (depends on 11) The method of claim 11, wherein the array of vertical pillars includes a plurality of vertical pillars used for memory cells in the strips continuous with the pad, and vertical pillars not used for memory cells disposed between the pad and the plurality of vertical pillars used for memory cells, comprising: a set of bit lines coupled to the plurality of vertical pillars used for memory cells in the strips continuous with the pad. ### Claim 16 (depends on 15) The method of claim 15, wherein the conductive strips extend in a first direction, the vertical pillars used for memory cells and the vertical pillars not used for memory cells have a common pitch and a common width in the first direction. ### Claim 17 (depends on 15) The method of claim 15, wherein the conductive strips extend in a first direction, the vertical pillars not used for memory cells have a different width in the first direction than the vertical pillars used for memory cells. ### Claim 18 (depends on 11) The method of claim 11, said etching comprising forming a second pad, wherein the strips continuous with the first-mentioned pad are separated from the second pad at ends proximal to the second pad, and strips continuous with the second pad are separated from the first-mentioned pad at ends proximal to the first-mentioned pad. ### Claim 19 (depends on 11) The method of claim 11, wherein the array of vertical pillars comprises a block of vertical pillars inside the array boundary, and a third pad disposed opposite the first-mentioned pad in a second direction orthogonal to a first direction along which the conductive strips extend, the method comprising: forming first and second boundary rows of vertical pillars extending in the first direction through the stack of patterned conductor layers, the first and second rows being disposed adjacent and spanning the first-mentioned pad and the block of vertical pillars, the vertical pillars in the first and second boundary rows are not used for memory cells; and forming a block isolation structure through the stack of patterned conductor layers separating the first-mentioned pad from the third pad, the vertical pillars in the first and second boundary rows in contact with sides of the block isolation structure. ### Claim 20 A 3D circuit, comprising: a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad; an array of circuit structures in the stack of patterned conductor layers, the array having an array boundary proximal to the pad; a first set of isolation blocks extending through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad; and a second set of isolation blocks inside the array boundary and extending through the plurality of patterned conductor layers isolating the other strips from the pad.