# US 2021/0242226 A1 · Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor

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- Number: US 2021/0242226 A1
- Document ID: US20210242226A1
- Status: Published application
- Kind: A1
- Application number: 17/235,343
- Filed: 2021-04-20
- Published: 2021-08-05
- Earliest claimed: 2017-06-29
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Durai Vishak Nirmal Ramaswamy
- Web page: https://patentgrep.com/patent/US20210242226A1

## CPC

- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/05: {Making the transistor}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/48: {Data lines or contacts therefor}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 1/692: {Electrodes}
- H10D 1/716: {having vertical extensions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/43: Layouts of interconnections
- H10B 51/10: characterised by the top-view layout
- H10B 51/30: characterised by the memory core region
- H10B 53/10: characterised by the top-view layout
- H10B 53/30: characterised by the memory core region
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 50/283: {by chemical means}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual of the channel regions that are in different of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual of the transistors in the different memory-cell tiers; and
a sense line electrically coupled to multiple of the second source/drain regions.

### Claim 22 (depends on 21)

The array of claim 21 comprising a horizontally-extending conductive strap that directly electrically couples the pair of access-line pillars together.

### Claim 23 (depends on 22)

The array of claim 22 comprising a horizontal longitudinally-elongated conductive line directly electrically coupled to the conductive strap of multiple of the pairs of access-line pillars.

### Claim 24 (depends on 22)

The array of claim 22 wherein the conductive strap is above the pair of access-line pillars.

### Claim 25 (depends on 24)

The array of claim 24 comprising a horizontal longitudinally-elongated conductive line directly electrically coupled to the conductive strap of multiple of the pairs of access-line pillars.

### Claim at position 7

26-30. (canceled)

### Claim 31

A method of forming a memory array, the memory array comprising memory cells individually comprising a transistor and a capacitor, the method comprising:
forming vertically-alternating tiers of insulative material and transistor material; the transistor-material tiers individually comprising a first source/drain region and a second source/drain region having a channel region horizontally there-between;
forming a pair of access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual of the channel regions that are in different of the transistor-material tiers, portions of the access-line pillars in the different transistor-material tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual of the transistors in the different transistor-material tiers;
forming a sense line electrically coupled to multiple of the second source/drain regions; and
forming capacitors individually comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to individual of the first source/drain regions, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another.

### Claim 32 (depends on 31)

The method of claim 31 comprising forming conductor material that directly electrically couples the pair of access-line pillars together.

### Claim 33 (depends on 32)

The method of claim 32 comprising forming the conductor material above the pair of access-line pillars.

### Claim 34 (depends on 33)

The method of claim 33 comprising forming a horizontal longitudinally-elongated conductive line above and directly electrically coupled to the conductor material of multiple of the pairs of access-line pillars.