# US 2021/0242225 A1 · Semiconductor structure and manufacturing method thereof

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- Number: US 2021/0242225 A1
- Document ID: US20210242225A1
- Status: Published application
- Kind: A1
- Application number: 16/857,074
- Filed: 2020-04-23
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: MAURICIO MANFRINI; SAI-HOOI YEONG; HAN-JONG CHIA; CHENCHEN JACOB WANG
- Web page: https://patentgrep.com/patent/US20210242225A1

## CPC

- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10D 64/689: {having ferroelectric layers}
- G11C 11/221: {using ferroelectric capacitors}
- H10D 1/684: {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10B 51/30: characterised by the memory core region
- H10B 53/10: characterised by the top-view layout
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a transistor disposed within the first dielectric layer; a second dielectric layer disposed over the first dielectric layer; and a capacitor disposed within the second dielectric layer and electrically connected to the transistor, wherein the capacitor includes a first electrode, a dielectric stack disposed over the first electrode, and a second electrode disposed over the dielectric stack, the dielectric stack includes a ferroelectric layer and an electrostrictive layer. Further, a method of manufacturing a semiconductor structure includes disposing an electrostrictive material over a first electrode layer; disposing a ferroelectric material over the first electrode layer; removing a portion of the ferroelectric material to form the ferroelectric material; and removing a portion of the electrostrictive material to form the electrostrictive layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
a first dielectric layer disposed over the substrate;
a transistor disposed within the first dielectric layer;
a second dielectric layer disposed over the first dielectric layer; and
a capacitor disposed within the second dielectric layer and electrically connected to the transistor,
wherein the capacitor includes a first electrode, a dielectric stack disposed over the first electrode, and a second electrode disposed over the dielectric stack, the dielectric stack includes a ferroelectric layer and an electrostrictive layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the ferroelectric layer contacts the electrostrictive layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the electrostrictive layer has a piezoelectric charge coefficient (d constant d33) substantially greater than a piezoelectric charge coefficient (d constant d33) of the ferroelectric layer.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the electrostrictive layer has a piezoelectric charge coefficient (d constant d33) substantially greater than 5 pico Coulomb/Newton (pC/N).

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the electrostrictive layer is disposed on the first electrode, and the ferroelectric layer is disposed on the electrostrictive layer.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the ferroelectric layer contacts the second electrode.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the ferroelectric layer is disposed on the first electrode, and the electrostrictive layer is disposed on the ferroelectric layer.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the electrostrictive layer contacts the second electrode.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a first conductive via disposed within the second dielectric layer and extending between the first electrode and a contact plug of a doped region of the transistor;
a second conductive via disposed within the second dielectric layer and disposed over and contacting the capacitor.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the electrostrictive layer is free of lead (Pb).

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein a thickness of the electrostrictive layer is substantially less than a thickness of the ferroelectric layer.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein a thickness of the electrostrictive layer is about 1 nm to about 5 nm.

### Claim 13

A semiconductor structure, comprising:
a substrate including a doped region;
a first dielectric layer disposed over the substrate;
a gate structure surrounded by the first dielectric layer and partially disposed over the doped region;
a second dielectric layer disposed over the first dielectric layer;
a conductive via disposed over and electrically connected to the doped region; and
a capacitor surrounded by the second dielectric layer and disposed over and electrically connected to the conductive via,
wherein the capacitor includes a first electrode over the conductive via, a dielectric stack disposed over the first electrode, and a second electrode disposed over the dielectric stack, the dielectric stack includes a plurality of ferroelectric layers and a plurality of electrostrictive layers.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the plurality of ferroelectric layers and the plurality of electrostrictive layers are alternately disposed.

### Claim 15 (depends on 13)

The semiconductor structure of claim 13, wherein each of the plurality of electrostrictive layers contacts at least one of the plurality of ferroelectric layers.

### Claim 16 (depends on 13)

The semiconductor structure of claim 13, further comprising:
a contact plug extending through the first dielectric layer, contacted with the doped region and electrically connected to the conductive via;
an isolation surrounding the dielectric stack and the second electrode.

### Claim 17

A method of manufacturing a semiconductor structure, comprising:
providing a substrate, a first dielectric layer over the substrate and a transistor surrounded by the first dielectric layer;
disposing a first electrode layer over the first dielectric layer;
disposing an electrostrictive material over the first electrode layer;
disposing a ferroelectric material over the first electrode layer;
disposing a second electrode layer over the electrostrictive material and the ferroelectric material;
disposing a patterned hardmask over the second electrode layer;
removing a portion of the ferroelectric material exposed from the patterned hardmask to form the ferroelectric layer; and
removing a portion of the electrostrictive material exposed from the patterned hardmask to form the electrostrictive layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the disposing of the electrostrictive material is performed before or after the disposing of the ferroelectric material.

### Claim 19 (depends on 17)

The method of claim 17, wherein the removal of the portion of the electrostrictive material and the removal of the portion of the ferroelectric material are performed simultaneously or separately.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
removing a portion of the first electrode layer exposed from the patterned hardmask to form a first electrode;
removing a portion of the second electrode layer exposed from the patterned hardmask to form a second electrode.