# US 2021/0242224 A1 · Semiconductor memory device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242224 A1 - Document ID: US20210242224A1 - Status: Published application - Kind: A1 - Application number: 16/936,203 - Filed: 2020-07-22 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jae Taek KIM; Hye Yeong JUNG - Web page: https://patentgrep.com/patent/US20210242224A1 ## CPC - H10B 20/60: {Peripheral circuit regions} - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B 63/34: {of the vertical channel field-effect transistor type} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell source structure; a first stack structure disposed on the cell source structure; a channel structure penetrating the first stack structure, the channel structure being connected to the cell source structure; and a first peripheral transistor including impurity regions. A level of a bottom surface of each of the impurity regions is higher than that of a bottom surface of the cell source structure, and a level of a top surface of each of the impurity regions is lower than that of a top surface of the cell source structure. ## Claims ### Claim 1 A semiconductor memory device comprising: a cell source structure; a first stack structure disposed on the cell source structure, the first stack structure including insulating patterns and conductive patterns, which are alternately stacked; a channel structure penetrating the first stack structure, the channel structure being connected to the cell source structure; and a first peripheral transistor including impurity regions and a gate structure, wherein a level of a bottom surface of each of the impurity regions is higher than that of a bottom surface of the cell source structure, and a level of a top surface of each of the impurity regions is lower than that of a top surface of the cell source structure. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the first peripheral transistor further includes a base part including a channel region, wherein the impurity regions are located at both sides of an upper portion of the base part, wherein the channel region is located between the impurity regions, wherein a level of a bottom surface of the base part is substantially equal to that of the bottom surface of the cell sourced structure. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein the first peripheral transistor further includes a base part including a channel region, wherein the base part includes the same material as the cell source structure. ### Claim 4 (depends on 3) The semiconductor memory device of claim 3, wherein the base part and the cell source structure include doped poly-silicon. ### Claim 5 (depends on 1) The semiconductor memory device of claim 1, wherein a level of a top surface of the gate structure is substantially equal to that of the top surface of the cell source structure. ### Claim 6 (depends on 1) The semiconductor memory device of claim 1, wherein the gate structure includes: gate spacers; a gate pattern between the gate spacers; and a gate interposition layer between the gate spacers. ### Claim 7 (depends on 6) The semiconductor memory device of claim 6, wherein the gate pattern includes the same material as the cell source structure. ### Claim 8 (depends on 7) The semiconductor memory device of claim 7, wherein the gate pattern and the cell source structure include doped poly-silicon. ### Claim 9 (depends on 6) The semiconductor memory device of claim 6, wherein the gate interposition layer includes a first interposition part, a second interposition part, and a third interposition part, which are sequentially stacked, wherein the second interposition part includes doped poly-silicon or undoped poly-silicon. ### Claim 10 (depends on 9) The semiconductor memory device of claim 9, wherein the first and third interposition parts include a same material and the second interposition part includes a material different from that of the first and third interposition parts. ### Claim 11 (depends on 6) The semiconductor memory device of claim 6, further comprising first contacts connected to the first peripheral transistor, wherein at least one of the first contacts penetrates the gate spacer and is connected to at least one of the impurity regions. ### Claim 12 A semiconductor memory device, comprising: a first peripheral transistor; a first insulating layer covering the first peripheral transistor; a cell source structure on the first insulating layer; a first stack structure disposed on the cell source structure, the first stack structure including first insulating patterns and conductive patterns, which are alternately stacked; a channel structure penetrating the first stack structure, the channel structure being connected to the cell source structure; and a second peripheral transistor on the first insulating layer, wherein the first peripheral transistor is disposed at a level lower than that of the cell source structure, and the second peripheral transistor is disposed at the same level as the cell source structure. ### Claim 13 (depends on 12) The semiconductor memory device of claim 12, wherein the first peripheral transistor and the second peripheral transistor overlap with each other. ### Claim 14 (depends on 12) The semiconductor memory device of claim 12, further comprising a second stack structure disposed on the second peripheral transistor, the second stack structure including second insulating patterns and sacrificial patterns, which are alternately stacked. ### Claim 15 (depends on 14) The semiconductor memory device of claim 14, further comprising first contacts connected to the second peripheral transistor, wherein the first contacts penetrate the second stack structure. ### Claim 16 (depends on 12) The semiconductor memory device of claim 12, wherein the second peripheral transistor includes an impurity region, wherein a level of a bottom surface of the impurity region is higher than that of the bottom surface of the cell source structure, and a level of a top surface of the impurity region is lower than that of the top surface of the cell source structure. ### Claim 17 (depends on 12) The semiconductor memory device of claim 12, further comprising a peripheral source structure between the second peripheral transistor and the cell source structure. ### Claim 18 (depends on 17) The semiconductor memory device of claim 17, further comprising a first spacer disposed between the second peripheral transistor and the peripheral source structure and a second spacer disposed between the peripheral source structure and the cell source structure. ### Claim 19 (depends on 17) The semiconductor memory device of claim 17, wherein the peripheral source structure includes a first source layer, a second source layer, and a third source layer between the first and second source layers, wherein the first and second source layers include the same material as the cell source structure.