# US 2021/0242222 A1 · Controlling trap formation to improve memory window in one-time prograrm devices

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- Number: US 2021/0242222 A1
- Document ID: US20210242222A1
- Status: Published application
- Kind: A1
- Application number: 16/781,274
- Filed: 2020-02-04
- Published: 2021-08-05
- Earliest claimed: 2020-02-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsin-Wen Su; Lien Jung Hung; Ping-Wei Wang; Yu-Kuan Lin; Shih-Hao Lin
- Web page: https://patentgrep.com/patent/US20210242222A1

## CPC

- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- G11C 17/146: {Write once memory, i.e. allowing changing of memory content by writing additional bits}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.

## Claims

### Claim 1

A one-time program (OTP) memory cell, comprising:
a read transistor comprising a read dielectric layer and a read gate electrode overlying the read dielectric layer; and
a program transistor neighboring the read transistor, wherein the program transistor comprises a program dielectric layer and a program gate electrode overlying the program dielectric layer,
wherein the program transistor has a smaller breakdown voltage than the read transistor.

### Claim 2 (depends on 1)

The OTP memory cell of claim 1, wherein a top surface of the read dielectric layer has a first average surface roughness, and wherein a top surface of the program dielectric layer has a second average surface roughness greater than the first average surface roughness.

### Claim 3 (depends on 1)

The OTP memory cell of claim 1, wherein the read and program transistors are arranged over a substrate, and further comprising:
a program interfacial layer arranged between the program dielectric layer and the substrate; and
a read interfacial layer arranged between the read dielectric layer and the substrate.

### Claim 4 (depends on 1)

The OTP memory cell of claim 1, wherein the program dielectric layer and the read dielectric layer comprise a same material.

### Claim 5 (depends on 1)

The OTP memory cell of claim 1, wherein the read dielectric layer has a first average thickness, and wherein the program dielectric layer has a second average thickness less than the first average thickness.

### Claim 6 (depends on 1)

The OTP memory cell of claim 1, wherein the program gate electrode and the read gate electrode comprise a same material.

### Claim 7 (depends on 1)

The OTP memory cell of claim 1, further comprising a shared source/drain region shared amongst the read transistor and the program transistor.

### Claim 8

A one-time program (OTP) memory cell, comprising:
a read transistor coupled in series with a program transistor over a substrate;
wherein the read transistor comprises a read dielectric layer arranged between a read gate electrode and the substrate;
wherein the program transistor comprises a program dielectric layer arranged between a program gate electrode and the substrate;
wherein the read dielectric layer has a first average surface roughness; and
wherein the program dielectric layer has a second average surface roughness that is greater than the first average surface roughness.

### Claim 9 (depends on 8)

The OTP memory cell of claim 8, wherein the read transistor has a greater breakdown voltage than the program transistor.

### Claim 10 (depends on 8)

The OTP memory cell of claim 8, wherein the read gate electrode comprises a different material than the program gate electrode.

### Claim 11 (depends on 8)

The OTP memory cell of claim 8, wherein the read dielectric layer comprises a first concentration of defects, and wherein the program dielectric layer comprises a second concentration of defects greater than the first concentration of defects.

### Claim 12 (depends on 8)

The OTP memory cell of claim 8, wherein the program dielectric layer directly contacts the program gate electrode, and wherein the read dielectric layer directly contacts the read gate electrode.

### Claim 13 (depends on 8)

The OTP memory cell of claim 8, wherein the program dielectric layer and the read dielectric layer both comprise a high-k dielectric material.

### Claim 14 (depends on 8)

The OTP memory cell of claim 8, wherein the program gate electrode is coupled to a program word-line, and wherein the read gate electrode is coupled to a read word-line.

### Claim 15

A method of forming a one-time program (OTP) memory cell, the method comprising:
forming a first dummy gate stack comprising a first dummy gate electrode over a program dielectric layer on a substrate;
forming a second dummy gate stack comprising a second dummy gate electrode over a read dielectric layer on the substrate;
forming a masking structure over the second dummy gate stack;
performing a first etching process to remove the first dummy gate electrode to expose the program dielectric layer;
removing the masking structure;
performing a second etching process to remove the second dummy gate electrode to expose the read dielectric layer, wherein the program dielectric layer is exposed to the second etching process; and
forming a program gate electrode over the program dielectric layer and a read gate electrode over the read dielectric layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein in the first etching process and the second etching process use a same plasma etchant.

### Claim 17 (depends on 16)

The method of claim 16, wherein the program dielectric layer is exposed to the same plasma etchant for a longer time period than the read dielectric layer.

### Claim 18 (depends on 15)

The method of claim 15, wherein before the first etching process, the program dielectric layer has a first average surface roughness, and wherein after the second etching process, the program dielectric layer has a second average surface roughness greater than the first average surface roughness.

### Claim 19 (depends on 18)

The method of claim 18, wherein the method further comprises:
forming an additional masking structure over the read gate electrode;
performing a third etching process to remove the program gate electrode to expose the program dielectric layer;
forming a second program gate electrode over the program dielectric layer, wherein the second program gate electrode comprises a different material than the read gate electrode; and
removing the additional masking structure.

### Claim 20 (depends on 19)

The method of claim 19, wherein after the second program gate electrode is formed on the program dielectric layer, the program dielectric layer has a third average surface roughness greater than the second average surface roughness.