# US 2021/0242220 A1 · Semiconductor device

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- Number: US 2021/0242220 A1
- Document ID: US20210242220A1
- Status: Published application
- Kind: A1
- Application number: 17/236,115
- Filed: 2021-04-21
- Published: 2021-08-05
- Earliest claimed: 2015-05-26
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei YAMAZAKI; Tomoaki ATSUMI; Yuta ENDO
- Web page: https://patentgrep.com/patent/US20210242220A1

## CPC

- H10B 43/35: with cell select transistors, e.g. NAND
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a plurality of transistors over the substrate,
wherein channel formation regions of the plurality of transistors are provided in a same oxide semiconductor,
wherein the plurality of transistors are provided in a direction perpendicular to the substrate, and
wherein the oxide semiconductor includes a plurality of c-axis aligned crystal parts.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a channel length direction of the plurality of transistors is in a direction perpendicular to a top surface of the substrate.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the substrate includes a silicon transistor, and the plurality of transistors are electrically connected to the silicon transistor.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor includes indium and zinc.

### Claim 5

A semiconductor device comprising:
a substrate;
a plurality of transistors over the substrate,
wherein channel formation regions of the plurality of transistors are provided in a same oxide semiconductor,
wherein the plurality of transistors are provided in a direction perpendicular to the substrate, and
wherein the oxide semiconductor includes a nanocrystal.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein a size of the nanocrystal is greater than or equal to 1 nm and less than or equal to 10 nm.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein a channel length direction of the plurality of transistors is in a direction perpendicular to a top surface of the substrate.

### Claim 8 (depends on 5)

The semiconductor device according to claim 5, wherein the substrate includes a silicon transistor, and the plurality of transistors are electrically connected to the silicon transistor.

### Claim 9 (depends on 5)

The semiconductor device according to claim 5, wherein the oxide semiconductor includes indium and zinc.