# US 2021/0242216 A1 · Interconnect and memory structures having reduced topography variation formed in the beol

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- Number: US 2021/0242216 A1
- Document ID: US20210242216A1
- Status: Published application
- Kind: A1
- Application number: 16/777,540
- Filed: 2020-01-30
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chih-Chao Yang; Baozhen Li; Raghuveer Reddy Patlolla; Cornelius Brown Peethala
- Web page: https://patentgrep.com/patent/US20210242216A1

## CPC

- H10B 12/50: {Peripheral circuit region structures}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10B 53/30: characterised by the memory core region
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/092: {by smoothing the dielectric parts}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Interconnect structures or memory structures are provided in the BEOL in which topography variation is reduced. Reduced topography variation is achieved by providing a structure that includes a first dielectric capping layer that has a planar topmost surface and/or a second dielectric capping layer that has a planar topmost surface. The first dielectric capping layer has a non-planar bottom surface that contacts both a recessed surface of an interconnect dielectric material layer and a planar topmost surface of at least one electrically conductive structure that is embedded in the interconnect dielectric material layer.

## Claims

### Claim 1

A structure comprising:
at least one electrically conductive structure partially embedded in an interconnect dielectric material layer, wherein the interconnect dielectric material layer has a recessed surface located laterally adjacent to the at least one electrically conductive structure;
a first dielectric capping layer located on the interconnect dielectric material layer and the at least one electrically conductive structure, wherein the first dielectric capping layer has a non-planar bottom surface that contacts both the recessed surface of the interconnect dielectric material layer and a planar topmost surface of the at least one electrically conductive structure;
a second dielectric capping layer located on the first dielectric capping layer, wherein the second dielectric capping layer has an entirely planar topmost surface; and
at least one metal-containing structure located in the first dielectric capping layer and the second dielectric capping layer, wherein the at least one metal-containing structure contacts the at least one electrically conductive structure.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the first dielectric capping layer has an undulating upper surface comprising recessed surfaces located above each recess surface of the interconnect dielectric material structure and planar surfaces located above the planar surface of the at least one electrically conductive structure.

### Claim 3 (depends on 2)

The structure of claim 2, wherein the second dielectric capping layer has a non-planar bottom surface that contacts the undulating upper surface of the first dielectric capping layer.

### Claim 4 (depends on 3)

The structure of claim 3, wherein the entirely planar topmost surface of the second dielectric capping layer is coplanar with a topmost surface of the at least one metal-containing structure.

### Claim 5 (depends on 4)

The structure of claim 4, wherein the at least one metal-containing structure is composed of at least one electrically conductive metal-containing material or a stack of electrically conductive metal-containing materials.

### Claim 6 (depends on 5)

The structure of claim 5, wherein the metal-containing structure is composed of elements of a ferroelectric memory (FE) stack, a resistive random access memory (ReRAM) stack, a magnetoresistive random access memory (MRAM) stack, or a phase change random access memory (PRAM) stack.

### Claim 7 (depends on 3)

The structure of claim 3, further comprising another interconnect dielectric material layer located on the entirely planar topmost surface of the second dielectric capping layer, wherein an upper portion of the at least one metal-containing structure is present in the another interconnect dielectric material, and wherein the another interconnect dielectric material layer has a topmost surface that is coplanar with a topmost surface of the at least one metal-containing structure.

### Claim 8 (depends on 7)

The structure of claim 7, wherein the at least one metal-containing structure is composed of at least one electrically conductive metal-containing material or a stack of electrically conductive metal-containing materials.

### Claim 9 (depends on 7)

The structure of claim 7, wherein the metal-containing structure is composed of elements of a ferroelectric memory (FE) stack, a resistive random access memory (ReRAM) stack, a magnetoresistive random access memory (MRAM) stack, or a phase change random access memory (PRAM) stack.

### Claim 10 (depends on 1)

The structure of claim 1, wherein the first dielectric capping layer has an entirely planar topmost surface, and the second dielectric capping layer has an entirely planar bottommost surface that contacts the entirely planar topmost surface of the first dielectric capping layer.

### Claim 11 (depends on 10)

The structure of claim 10, wherein the entirely planar topmost surface of the second dielectric capping layer is coplanar with a topmost surface of the at least one metal-containing structure.

### Claim 12 (depends on 11)

The structure of claim 11, wherein the at least one metal-containing structure is composed of at least one electrically conductive metal-containing material or a stack of electrically conductive metal-containing materials.

### Claim 13 (depends on 11)

The structure of claim 11, wherein the metal-containing structure is composed of elements of a ferroelectric memory (FE) stack, a resistive random access memory (ReRAM) stack, a magnetoresistive random access memory (MRAM) stack, or a phase change random access memory (PRAM) stack.

### Claim 14 (depends on 11)

The structure of claim 11, further comprising another interconnect dielectric material layer located on the entirely planar topmost surface of the second dielectric capping layer, wherein an upper portion of the at least one metal-containing structure is present in the another interconnect dielectric material, and wherein the another interconnect dielectric material layer has a topmost surface that is coplanar with a topmost surface of the at least one metal-containing structure.

### Claim 15 (depends on 14)

The structure of claim 14, wherein the at least one metal-containing structure is composed of at least one electrically conductive metal-containing material or a stack of electrically conductive metal-containing materials.

### Claim 16 (depends on 14)

The structure of claim 14, wherein the metal-containing structure is composed of elements of a ferroelectric memory (FE) stack, a resistive random access memory (ReRAM) stack, a magnetoresistive random access memory (MRAM) stack, or a phase change random access memory (PRAM) stack.

### Claim 17

A structure comprising:
at least one electrically conductive structure partially embedded in an interconnect dielectric material layer, wherein the interconnect dielectric material layer has a recessed surface located laterally adjacent to the at least one electrically conductive structure;
a first dielectric capping layer located on the recessed surface of the interconnect dielectric material and the at least one electrically conductive structure, wherein the first dielectric capping layer has an entirely planar topmost surface and non-planar bottom surface that contacts both the recessed surface of the interconnect dielectric material layer and a planar topmost surface of the at least one electrically conductive structure; and
at least one metal-containing structure located in the first dielectric capping layer, wherein the at least one metal-containing structure contacts the at least one electrically conductive structure.

### Claim 18 (depends on 17)

The structure of claim 17, wherein the at least one metal-containing structure has a topmost surface that is coplanar with the entirely planar topmost surface of the first dielectric capping layer.

### Claim 19 (depends on 18)

The structure of claim 18, further comprising another interconnect dielectric material layer located on the entirely planar topmost surface of the first dielectric capping layer, wherein an upper portion of the at least one metal-containing structure is present in the another interconnect dielectric material, and wherein the another interconnect dielectric material layer has a topmost surface that is coplanar with a topmost surface of the at least one metal-containing structure.

### Claim 20 (depends on 17)

The structure of claim 17, wherein the at least one electrically conductive metal-containing structure is composed of at least one electrically conductive metal-containing material, a stack of electrically conductive metal-containing materials, elements of a ferroelectric memory (FE) stack, element of a resistive random access memory (ReRAM) stack, element of a magnetoresistive random access memory (MRAM) stack, or element of a phase change random access memory (PRAM) stack.