# US 2021/0242210 A1 · Memory device

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- Number: US 2021/0242210 A1
- Document ID: US20210242210A1
- Status: Published application
- Kind: A1
- Application number: 16/939,802
- Filed: 2020-07-27
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Ki Hong LEE
- Web page: https://patentgrep.com/patent/US20210242210A1

## CPC

- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- H10B 12/31: {having a storage electrode stacked over the transistor}
- G11C 11/408: Address circuits
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/05: {Making the transistor}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory cell includes a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor provided with an active region that is laterally oriented in a second direction crossing the bit line and includes a first active cylinder, a second active cylinder, and at least one channel portion oriented laterally between the first active cylinder and the second active cylinder; a word line extending in a third direction while surrounding the at least one channel portion of the active region; and a capacitor oriented laterally in the second direction between the active region and the plate line.

## Claims

### Claim 1

A memory cell, comprising:
a bit line and a plate line spaced apart from each other and vertically oriented in a first direction;
a transistor provided with an active region laterally oriented in a second direction to cross the bit line and including a first active cylinder, a second active cylinder, and at least one channel portion oriented laterally between the first active cylinder and the second active cylinder;
a word line extending in a third direction while surrounding the at least one channel portion of the active region; and
a capacitor oriented laterally in the second direction between the active region and the plate line.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the first active cylinder, the second active cylinder and the at least one channel portion are positioned in a lateral arrangement in the second direction.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein the word line includes:
a surrounding gate electrode surrounding the at least one channel portion; and
a first buried gate electrode extending from one side of the surrounding gate electrode and buried in the first active cylinder; and
a second buried gate electrode extending from another side of the surrounding gate electrode and buried in the second active cylinder.

### Claim 4 (depends on 3)

The memory cell of claim 3, wherein the active region includes a buried channel that is defined by the first buried gate electrode and the second buried gate electrode.

### Claim 5 (depends on 1)

The memory cell of claim 1, further comprising:
a vertical source region between the capacitor and the first active cylinder; and
a vertical drain region between the second active cylinder and the bit line.

### Claim 6 (depends on 1)

The memory cell of claim 1, further comprising:
a gate dielectric layer formed between the word line and the active region.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein the capacitor includes:
a cylinder-shape storage node coupled to the first active cylinder of the active region;
a plate node coupled to the plate line; and
a dielectric material between the storage node and the plate node,
wherein the storage node, the dielectric material, and the plate node are positioned in a lateral arrangement in the second direction.

### Claim 8 (depends on 7)

The memory cell of claim 7, wherein the plate node includes:
an internal node that is laterally oriented from the plate line and extends into the storage node; and
a plurality of external nodes that are laterally oriented from the plate line and surround the storage node.

### Claim 9 (depends on 8)

The memory cell of claim 8, wherein the external node includes:
first and second external nodes positioned over the storage node in the first direction; and
third and fourth external nodes positioned over the storage node in the third direction,
wherein the lateral lengths of the first external node and the second external node are shorter than the lateral lengths of the third external node and the fourth external node.

### Claim 10 (depends on 9)

The memory cell of claim 9,
wherein a lateral length of the first external node and a lateral length of the second external node are the same, and
a lateral length of the third external node and a lateral length of the fourth external node are the same.

### Claim 11 (depends on 1)

The memory cell of claim 1, wherein the first active cylinder and the second active cylinder are positioned at the same level and have cylinder-shapes that are laterally oriented to be opposite to each other in the second direction.

### Claim 12 (depends on 1)

The memory cell of claim 1, wherein the lateral length of the first active cylinder in the second direction is different from the lateral length of the second active cylinder in the second direction.

### Claim 13 (depends on 1)

The memory cell of claim 1, wherein the at least one channel portion includes
edges contacting the first active cylinder and the second active cylinder, and
a channel body between the edges,
wherein contact surfaces between the channel body and the edges are smaller than contact surfaces between the first and second active cylinders, and the edges.

### Claim 14 (depends on 13)

The memory cell of claim 13, wherein the at least one channel portion has a thickness that gradually decreases from the edges toward the channel body.

### Claim 15 (depends on 1)

The memory cell of claim 1,
wherein the first active cylinder includes a laterally oriented first recessed portion, and the second active cylinder includes a laterally oriented second recessed portion, and
wherein the laterally oriented first recessed portion and the laterally oriented second recessed portion are opposite to each other in the second direction.

### Claim 16 (depends on 15)

The memory cell of claim 15, wherein the first active cylinder is positioned between the capacitor and the laterally oriented first recessed portion, and includes a first vertical side wall that is coupled to the capacitor.

### Claim 17 (depends on 15)

The memory cell of claim 15, wherein the second active cylinder is positioned between the bit line and the laterally oriented second recessed portion, and includes a second vertical side wall that is coupled to the bit line.

### Claim 18 (depends on 1)

The memory cell of claim 1, further comprising:
a vertical source region between the capacitor and the first active cylinder; and
a vertical drain region between the second active cylinder and bit line.