# US 2021/0242209 A1 · Dynamic random access memory device and manufacturing method thereof

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- Number: US 2021/0242209 A1
- Document ID: US20210242209A1
- Status: Published application
- Kind: A1
- Application number: 17/166,583
- Filed: 2021-02-03
- Published: 2021-08-05
- Earliest claimed: 2020-02-03
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Cheol-Soo PARK; Ming-Tang CHEN
- Web page: https://patentgrep.com/patent/US20210242209A1

## CPC

- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10D 1/716: {having vertical extensions}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/318: {the storage electrode having multiple segments}
- H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching}
- H10D 1/714: {having horizontal extensions}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A DRAM device and its manufacturing method are provided. The DRAM device includes an interlayer dielectric layer and capacitor units framed on a substrate. The interlayer dielectric layer has capacitor unit accommodating through holes and includes a first support layer, a composite dielectric layer, and a second support layer sequentially formed on the substrate. The composite dielectric layer includes at least one first insulating layer and second insulating layer alternately stacked. Each capacitor unit accommodating through hole forms a first opening in the second insulating layer and forms a second opening communicating with the first opening in the first insulating layer. The second opening is wider than the first opening. The capacitor units are formed in the capacitor unit accommodating through holes. The top of the capacitor unit is higher than the top surface of the interlayer dielectric layer and defines a recessed region.

## Claims

### Claim 1

A dynamic random access memory (DRAM) device, comprising:
a substrate;
an interlayer dielectric layer formed on the substrate, wherein the interlayer dielectric layer has a plurality of capacitor unit accommodating through holes, and each of the capacitor unit accommodating through holes penetrates the interlayer dielectric layer, wherein the interlayer dielectric layer comprises:
a first support layer formed on the substrate;
a composite dielectric layer formed on the first support layer, wherein the composite dielectric layer comprises at least one first insulating layer and at least one second insulating layer alternately stacked, wherein each of the capacitor unit accommodating through holes forms a first opening in the second insulating layer and forms a second opening communicating with the first opening in the first insulating layer, and wherein a width of the second opening is greater than a width of the first opening; and
a second support layer formed on the composite dielectric layer;
a plurality of capacitor units formed in the capacitor unit accommodating through holes, wherein tops of the capacitor units are higher than a top surface of the interlayer dielectric layer, and the tops of the capacitor units define a recessed region; and
a first conductive layer formed between the substrate and the interlayer dielectric layer, wherein the first conductive layer has a plurality of third openings communicating with the capacitor unit accommodating through holes, and the capacitor units further formed in the third opening.

### Claim 2 (depends on 1)

The DRAM device as claimed in claim 1, further comprising:
a second conductive layer formed on the capacitor units and filling the recessed region, wherein the second conductive layer has a flat top surface.

### Claim 3 (depends on 1)

The DRAM device as claimed in claim 1, further comprising a plurality of contact structures formed under the first conductive layer,
wherein the capacitor units comprise a plurality of bottom electrode structures, wherein the bottom electrode structures are conformally formed on the surfaces of the capacitor unit accommodating through holes and surfaces of the third openings, and tops of the bottom electrode structures are higher than the top surface of the interlayer dielectric layer, and wherein each of the contact structures is electrically connected to one of the bottom electrode structures through the first conductive layer above each of the contact structures,
wherein the contact structures do not overlap with the bottom electrode structures located in the third openings.

### Claim 4 (depends on 3)

The DRAM device as claimed in claim 3, wherein two of the bottom electrode structures are located in each of the capacitor unit accommodating through holes.

### Claim 5 (depends on 3)

The DRAM device as claimed in claim 3, wherein the capacitor units further comprise:
a dielectric layer conformally formed on surfaces of the bottom electrode structures and the top surface of the interlayer dielectric layer; and
a top electrode structure conformally formed on a surface of the dielectric layer, wherein a top of the top electrode structure defines the recessed region, and the recessed region is located between tops of two of the bottom electrode structures formed in different capacitor unit accommodating through holes.

### Claim 6 (depends on 5)

The DRAM device as claimed in claim 5, further comprising:
a second conductive layer formed on the capacitor units and filling the recessed region, wherein the second conductive layer has a flat top surface,
wherein a material of the second conductive layer is different from a material of the top electrode structure.

### Claim 7 (depends on 5)

The DRAM device as claimed in claim 5, wherein a material of the top electrode structure comprises titanium nitride or titanium silicon nitride.

### Claim 8 (depends on 2)

The DRAM device as claimed in claim 2, wherein a material of the second conductive layer comprises silicon germanium or silicon germanium boron compound.

### Claim 9 (depends on 1)

The DRAM device as claimed in claim 1, wherein the first support layer has a first thickness, the second support layer has a second thickness, and a ratio of the second thickness to the first thickness is 1.5-10.0.

### Claim 10 (depends on 1)

The DRAM device as claimed in claim 1, wherein a material of the first insulating layer is oxide, a material of the second insulating layer is nitride, and a thickness of the first support layer is greater than a thickness of the second insulating layer.

### Claim 11

A method for manufacturing a DRAM device, comprising:
forming a first conductive layer over a substrate;
forming an interlayer dielectric layer on the first conductive layer, wherein the interlayer dielectric layer has a plurality of capacitor unit accommodating through holes, and each of the capacitor unit accommodating through holes penetrates the interlayer dielectric layer, wherein forming the interlayer dielectric layer comprises:
forming a first support layer on the substrate;
forming a composite dielectric layer on the first support layer, wherein the composite dielectric layer comprises at least one first insulating layer and at least one second insulating layer alternately stacked, wherein each of the capacitor unit accommodating through holes forms a first opening in the second insulating layer and forms a second opening communicating with the first opening in the first insulating layer, and wherein a width of the second opening is greater than a width of the first opening; and
forming a second support layer on the composite dielectric layer; and
forming a plurality of capacitor units in the capacitor unit accommodating through holes, wherein tops of the capacitor units are higher than a top surface of the interlayer dielectric layer, and the tops of the capacitor units define a recessed region,
wherein the first conductive layer has a plurality of third openings communicating with the capacitor unit accommodating through holes, and the capacitor units further formed in the third opening.

### Claim 12 (depends on 11)

The method for manufacturing the DRAM device as claimed in claim 11, further comprising:
forming a contact structure in the substrate; and
forming a stress adjustment layer on the second support layer, wherein a material of the stress adjustment layer comprises silicon oxynitride, silicon oxide, or silicon nitride.

### Claim 13 (depends on 12)

The method for manufacturing the DRAM device as claimed in claim 12, wherein forming the capacitor unit comprises:
performing a first etching process to form the first opening penetrating the stress adjustment layer, the second support layer, the at least one first insulating layer, the at least one second insulating layer, and the first support layer;
performing a second etching process to remove a portion of the first insulating layer and form the second opening in the first insulating layer;
performing a third etching process to form the third opening in the first conductive layer;
conformally forming a bottom electrode material on surfaces of the capacitor unit accommodating through holes, a surface of the third opening, and a surface of the stress adjustment layer;
performing a fourth etching process to remove the bottom electrode material located on a bottom surface of the third opening and a top surface of the stress adjustment layer, so that a plurality of bottom electrode structures are formed, wherein the contact structure is electrically connected to one of the bottom electrode structures through the first conductive layer above the contact structure;
performing a fifth etching process to remove the stress adjustment layer, so that the plurality of bottom electrode structures protrude beyond the second support layer;
conformally forming a dielectric layer on the plurality of bottom electrode structures, the bottom surface of the third opening, and a top surface of the second support layer;
conformally forming a top electrode structure on the dielectric layer, wherein the top electrode structure the capacitor unit accommodating through holes, and wherein a top of the top electrode structure defines a recessed region.

### Claim 14 (depends on 13)

The method for manufacturing the DRAM device as claimed in claim 13, further comprising:
forming a second conductive layer on the capacitor units and filling the recessed region, wherein the second conductive layer has a flat top surface.

### Claim 15 (depends on 13)

The method for manufacturing the DRAM device as claimed in claim 13, wherein during the second etching process, a ratio of the etching rate of the first insulating layer to the etching rate of the second insulating layer is 10-100.

### Claim 16 (depends on 13)

The method for manufacturing the DRAM device as claimed in claim 13, wherein during the fifth etching process, a ratio of the etching rate of the stress adjustment layer to the etching rate of the second support layer is 10-100.

### Claim 17 (depends on 13)

The method for manufacturing the DRAM device as claimed in claim 13, wherein the dielectric layer and the top electrode structure is formed by an atomic layer deposition process.

### Claim 18 (depends on 13)

The method for manufacturing the DRAM device as claimed in claim 13, wherein the contact structure does not overlap with the bottom electrode structures located in the third openings.

### Claim 19 (depends on 14)

The method for manufacturing the DRAM device as claimed in claim 14, wherein a material of the second conductive layer is different from a material of the top electrode structure.

### Claim 20 (depends on 19)

The method for manufacturing the DRAM device as claimed in claim 19, wherein a material of the second conductive layer comprises silicon germanium or silicon germanium boron compound.