# US 2021/0242204 A1 · Composite transistor

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- Number: US 2021/0242204 A1
- Document ID: US20210242204A1
- Status: Published application
- Kind: A1
- Application number: 17/233,753
- Filed: 2021-04-19
- Published: 2021-08-05
- Earliest claimed: 2016-05-11
- Assignees: Sony Group Corporation
- Applicants: Sony Group Corporation
- Inventors: Koichi MATSUMOTO
- Web page: https://patentgrep.com/patent/US20210242204A1

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10D 12/211: {Gated diodes}
- H10D 30/01: Manufacture or treatment
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/8303: {Diamond}
- H10D 62/882: {Graphene}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 62/82: Heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Disclosed herein is a composite transistor which includes a first transistor TR1 including a control electrode, a first active region, a first A extending part, and a first B extending part, and a second transistor TR2 including a control electrode, a second active region, a second A extending part, and a second B extending part. The first active region, the second active region, and the control electrode overlap one another. Both the first A extending part and the first B extending part extend from the first active region and both the second A extending part and the second B extending part extend from the second active region. The first electrode is connected to the first A extending part, the second electrode is connected to the second A extending part, and the third electrode is connected to the first B extending part and the second B extending part.

## Claims

### Claim 1

A composite transistor, comprising:
a control electrode;
a first electrode;
a second electrode;
a third electrode;
a first A extending part, wherein the first A extending part extends from the first electrode to a first A active region;
a second A extending part, wherein the second A extending part extends from the second electrode to a second A active region;
a first B extending part, wherein the first B extending part extends from the third electrode to a first B active region;
a second B extending part, wherein the second B extending part extends from the third electrode to a second B active region.

### Claim 2 (depends on 1)

The composite transistor according to claim 1, wherein the control electrode, the first B active region, and the first A active region, and second B active region, and the second A active region are stacked with one another, with the first B active region between the control electrode and the first A active region, with the first A active region between the first B active region and the second B active region, and with the second B active region between the first A active region and the second A active region.

### Claim 3 (depends on 2)

The composite transistor according to claim 2, wherein an insulating layer is disposed between the control electrode and the first B active region.

### Claim 4 (depends on 1)

The composite transistor according to claim 1, wherein the first A active region and the first B active region are disposed on a first virtual plane, and wherein a first boundary region disposed on the first virtual plane is interposed between the first A active region and the first B active region.

### Claim 5 (depends on 4)

The composite transistor according to claim 4, wherein the second A active region and the second B active region are disposed on a second virtual plane, and wherein a second boundary region disposed on the second virtual plane is interposed between the second A active region and the second B active region.

### Claim 6 (depends on 5)

The composite transistor according to claim 5, wherein the first boundary region is between the control electrode and the second boundary region.

### Claim 7 (depends on 6)

The composite transistor according to claim 6, wherein the first A active region and the first B active region are in contact with each other, and wherein the second A active region and the second B active region are not in contact with each other.

### Claim 8 (depends on 1)

The composite transistor according to claim 1, wherein the first transistor becomes conductive and the second transistor becomes non-conductive when the first electrode is given a voltage higher than a voltage given to the second electrode and the control electrode is given a first voltage, and the second transistor becomes conductive and the first transistor becomes non-conductive when the control electrode is given a second voltage higher than the first voltage.

### Claim 9 (depends on 1)

The composite transistor according to claim 1, wherein the first active region and the second active region include a two-dimensional material or graphene.

### Claim 10 (depends on 1)

The composite transistor of claim 1, wherein a second insulation layer is provided between the first active region and the second active region.

### Claim 11 (depends on 4)

The composite transistor according to claim 4, wherein the first active region and the second active region include a two-dimensional material or graphene.

### Claim 12 (depends on 11)

The composite transistor according to claim 11,
wherein a first interlayer insulation layer is provided between the first A active region and the first B active region, and
a second interlayer insulation layer is provided between the second A active region and the second B active region.

### Claim 13 (depends on 10)

The composite transistor according to claim 10,
wherein a first interlayer insulation layer is provided between the first A active region and the first B active region, and
a second interlayer insulation layer is provided between the second A active region and the second B active region.

### Claim 14

A composite transistor, comprising:
a control electrode;
a first electrode;
a second electrode;
a third electrode;
a first A extending part, wherein the first A extending part extends from the first electrode to a first channel forming region;
a second A extending part, wherein the second A extending part extends from the second electrode to a second channel forming region;
a first B extending part, wherein the first B extending part extends from the third electrode to the first channel forming region;
a second B extending part, wherein the second B extending part extends from the third electrode to the second channel forming region.

### Claim 15 (depends on 14)

The composite transistor according to claim 14, wherein the first channel forming region is disposed on a first virtual plane, and wherein the second channel forming region is disposed on a second virtual plane.

### Claim 16 (depends on 15)

The composite transistor according to claim 15, wherein the first channel forming region is disposed between the control electrode and the second channel forming region.

### Claim 16 (depends on 14)

The composite transistor according to claim 14, wherein the first transistor becomes conductive and the second transistor becomes non-conductive when the first electrode is given a voltage higher than a voltage given to the second electrode and the control electrode is given a first voltage, and the second transistor becomes conductive and the first transistor becomes non-conductive when the control electrode is given a second voltage higher than the first voltage.

### Claim 17 (depends on 14)

The composite transistor of claim 14, wherein the first active region and the second active region include a two-dimensional material or graphene.

### Claim 18 (depends on 14)

The composite transistor according to claim 14, wherein a second insulation layer is provided between the first active region and the second active region.

### Claim 19 (depends on 18)

The composite transistor of claim 18, wherein the first active region and the second active region include a two-dimensional material or graphene.