# US 2021/0242202 A1 · Integrated circuit devices including vertical field-effect transistors

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- Number: US 2021/0242202 A1
- Document ID: US20210242202A1
- Status: Published application
- Kind: A1
- Application number: 16/947,692
- Filed: 2020-08-13
- Published: 2021-08-05
- Earliest claimed: 2020-02-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: JUNG HO DO; SEUNG HYUN SONG
- Web page: https://patentgrep.com/patent/US20210242202A1

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/635: {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 89/10: Integrated device layouts
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/937: {Implementation of digital circuits}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Integrated circuit devices including standard cells are provided. The standard cells may include a first vertical field effect transistor (VFET) including a first channel region and having a first conductivity type and a second VFET including a second channel region and having a second conductivity type that is different from the first conductivity type. Each of the first channel region and the second channel region may extend longitudinally in a first horizontal direction, and the first channel region may be spaced apart from the second channel region in a second horizontal direction that is perpendicular to the first horizontal direction.

## Claims

### Claim 1

A standard cell comprising:
a first vertical field effect transistor (VFET) comprising a first channel region and having a first conductivity type; and
a second VFET comprising a second channel region and having a second conductivity type that is different from the first conductivity type,
wherein each of the first channel region and the second channel region extends longitudinally in a first horizontal direction, and
the first channel region is spaced apart from the second channel region in a second horizontal direction that is perpendicular to the first horizontal direction.

### Claim 2 (depends on 1)

The standard cell of claim 1 further comprising:
a common gate layer comprising a first portion that is a first gate electrode of the first VFET, a second portion that is a second gate electrode of the second VFET, and a third portion that continuously extends from the first portion of the common gate layer to the second portion of the common gate layer; and
a gate contact that contacts the third portion of the common gate layer.

### Claim 3 (depends on 2)

The standard cell of claim 2 further comprising a gate via and a gate wire, wherein the gate via and the gate wire are sequentially stacked on the gate contact in a vertical direction, and the gate wire is electrically connected to the common gate layer and extends longitudinally in the second horizontal direction.

### Claim 4 (depends on 1)

The standard cell of claim 1, wherein the first VFET further comprises a first bottom source/drain region in a substrate, and the second VFET further comprises a second bottom source/drain region in the substrate, and
wherein the standard cell further comprises:
a first bottom contact contacting the first bottom source/drain region and extending parallel to the first channel region, wherein the first bottom contact is electrically connected to a drain voltage or a source voltage; and
a second bottom contact contacting the second bottom source/drain region and extending parallel to the second channel region.

### Claim 5 (depends on 4)

The standard cell of claim 4, wherein each of the first bottom contact and the second bottom contact extends longitudinally in the first horizontal direction.

### Claim 6 (depends on 1)

The standard cell of claim 1, wherein the first VFET further comprises a first bottom source/drain region in a substrate and a first top source/drain region on the first channel region, wherein the first bottom source/drain region, the first channel region, and the first top source/drain region are sequentially stacked on the substrate, and
wherein the second VFET further comprises a second bottom source/drain region in the substrate and a second top source/drain region on the second channel region, wherein the second bottom source/drain region, the second channel region, and the second top source/drain region are sequentially stacked on the substrate.

### Claim 7 (depends on 6)

The standard cell of claim 6 further comprising an output wire that is electrically connected to the first top source/drain region and the second top source/drain region and extends longitudinally in the second horizontal direction.

### Claim 8 (depends on 1)

The standard cell of claim 1 further comprising a third VFET comprising a third channel region and having the first conductivity type, wherein the third channel region extends longitudinally in the second horizontal direction.

### Claim 9 (depends on 8)

The standard cell of claim 8 further comprising a first bottom source/drain region in a substrate,
wherein the first channel region and the third channel region are electrically connected to the first bottom source/drain region.

### Claim 10 (depends on 1)

The standard cell of claim 1, wherein the first channel region comprises two first channel regions that are spaced apart from each other in the second horizontal direction.

### Claim 11 (depends on 10)

The standard cell of claim 10, wherein each of the two first channel regions extends longitudinally in the first horizontal direction.

### Claim 12

A standard cell comprising:
a first vertical field effect transistor (VFET) comprising a first bottom source/drain region in a substrate, a first channel region and a first top source/drain region sequentially stacked on the first bottom source/drain region in a vertical direction, wherein the first top source/drain region has a first conductivity type;
a second VFET comprising a second bottom source/drain region in the substrate, a second channel region and a second top source/drain region sequentially stacked on the second bottom source/drain region in the vertical direction, wherein the second top source/drain region has a second conductivity type that is different from the first conductivity type;
a common gate layer comprising a first portion that is on a side surface of the first channel region and is a first gate electrode of the first VFET and a second portion that is on a side surface of the second channel region and is a second gate electrode of the second VFET; and
a gate contact that is between the first channel region and the second channel region and contacts the common gate layer,
wherein each of the first channel region and the second channel region extends longitudinally in a first horizontal direction, and
the gate contact is spaced apart from the first channel region in a second horizontal direction that is perpendicular to the first horizontal direction.

### Claim 13 (depends on 12)

The standard cell of claim 12 further comprising a gate via and a gate wire, wherein the gate via and the gate wire are sequentially stacked on the gate contact in the vertical direction, and the gate wire is electrically connected to the common gate layer and extends longitudinally in the second horizontal direction.

### Claim 14 (depends on 12)

The standard cell of claim 12 further comprising an output wire that is electrically connected to the first top source/drain region and the second top source/drain region and extends longitudinally in the second horizontal direction.

### Claim 15 (depends on 12)

The standard cell of claim 12 further comprising:
a first bottom contact contacting the first bottom source/drain region and extending parallel to the first channel region, wherein the first bottom contact is electrically connected to a drain voltage or a source voltage; and
a second bottom contact contacting the second bottom source/drain region and extending parallel to the second channel region,
wherein each of the first bottom contact and the second bottom contact extends longitudinally in the first horizontal direction.

### Claim 16 (depends on 12)

The standard cell of claim 12 further comprising a third VFET that comprises a third channel region and a third top source/drain region and has the first conductivity type,
wherein the third channel region and the third top source/drain region are sequentially stacked on the first bottom source/drain region, and
the third channel region extends longitudinally in the second horizontal direction.

### Claim 17

A standard cell comprising:
a first vertical field effect transistor (VFET) having a first conductivity type, wherein the first VFET comprises two first channel regions that are spaced apart from each other in a first horizontal direction; and
a second VFET having a second conductivity type that is different from the first conductivity type, wherein the second VFET comprises a second channel region, and the second channel region is spaced apart from the two first channel regions in the first horizontal direction.

### Claim 18 (depends on 17)

The standard cell of claim 17, wherein each of the two first channel regions extend longitudinally in a second horizontal direction that is perpendicular to the first horizontal direction.

### Claim 19 (depends on 17)

The standard cell of claim 17 further comprising:
a common gate layer comprising a first portion that is a first gate electrode of the first VFET, a second portion that is a second gate electrode of the second VFET, and a third portion that continuously extends from the first portion of the common gate layer to the second portion of the common gate layer; and
a gate contact that contacts the third portion of the common gate layer.

### Claim 20 (depends on 19)

The standard cell of claim 19 further comprising a gate via and a gate wire,
wherein the gate via and the gate wire are sequentially stacked on the gate contact in a vertical direction, and
the gate wire is electrically connected to the common gate layer and extends longitudinally in the first horizontal direction.