# US 2021/0242200 A1 · Normally off iii nitride transistor

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- Number: US 2021/0242200 A1
- Document ID: US20210242200A1
- Status: Published application
- Kind: A1
- Application number: 17/234,385
- Filed: 2021-04-19
- Published: 2021-08-05
- Earliest claimed: 2015-03-30
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Qhalid Fareed; Naveen Tipirneni
- Web page: https://patentgrep.com/patent/US20210242200A1

## CPC

- H10D 84/84: Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 84/01: Manufacture or treatment
- H10D 84/0163: {the components including enhancement-mode IGFETs and depletion-mode IGFETs}
- H10D 84/05: using Group III-V technology
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10P 50/246: {of Group III-V materials}
- H10P 50/646: {of Group III-V materials}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10P 14/6312: {of Group III-V semiconductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a buffer layer;
a first III-N material over the buffer layer;
a second III-N material over the first III-N material;
a third III-N material disposed over the second III-N material, the third III-N having less than 1 atomic percent indium;
an indium aluminum nitride layer over the third III-N, the indium aluminum nitride layer having a stoichiometry of In0.05Al0.95N to In0.30Al0.70N, and a thickness of 1 nanometer to 5 nanometers;
a cap layer of III-N material disposed over the indium aluminum nitride layer;
a gate recess extending through the cap layer and the indium aluminum nitride layer in an enhancement mode gallium nitride field effect transistor (GaN FET), wherein the gate recess does not extend through the third III-N;
a gate dielectric layer disposed over the third III-N in the gate recess; and
a gate of the enhancement mode GaN FET disposed over the gate dielectric layer in the gate recess.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the third III-N has a stoichiometry of Al0.10Ga0.90N to Al0.30Ga0.70N, and a thickness of 1 nanometer to 5 nanometers.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the indium aluminum nitride layer has a stoichiometry of In0.16Al0.84N to In0.18Al0.82N and a thickness of 3.5 nanometers to 4.5 nanometers.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the cap layer has a stoichiometry of Al0.05Ga0.95N to Al0.30Ga0.70N, and a thickness of 4 nanometers to 20 nanometers.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, or aluminum oxide.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate comprises polysilicon.

### Claim 7

A semiconductor device, comprising:
a buffer layer;
a first GaN layer over the buffer layer;
a second GaN layer over the first GaN layer;
a first AlGaN layer disposed over the second GaN layer, the first AlGaN layer having less than 1 atomic percent indium;
an indium aluminum nitride layer over the AlGaN layer;
a second AlGaN layer disposed over the indium aluminum nitride layer;
a gate recess extending through the second AlGaN layer and the indium aluminum nitride layer in an enhancement mode GaN FET, wherein the gate recess does not extend through the first AlGaN layer;
a gate dielectric layer of the enhancement mode GaN FET disposed over the first AlGaN layer in the gate recess; and
a gate of the enhancement mode GaN FET disposed over the gate dielectric layer in the gate recess.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising:
a gate dielectric layer of a depletion mode GaN FET disposed over the second AlGaN layer, the indium aluminum nitride layer and the first AlGaN layer; and
a gate of the depletion mode GaN FET disposed over the gate dielectric layer of the depletion mode GaN FET.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein:
the gate dielectric layer of the enhancement mode GaN FET and the gate dielectric layer of the depletion mode GaN FET have substantially equal thicknesses and compositions; and
the gate of the enhancement mode GaN FET and the gate of the depletion mode GaN FET have substantially equal compositions.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the gate dielectric layer of the enhancement mode GaN FET and the gate dielectric layer of the depletion mode GaN FET comprise a material selected from the group consisting of silicon dioxide, silicon nitride, or aluminum oxide.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the gate of the enhancement mode GaN FET and the gate of the depletion mode GaN FET comprise polysilicon.

### Claim at position 12 (depends on 7)

12: The semiconductor device of claim 7, wherein the first AlGaN layer has a stoichiometry of Al0.10Ga0.90N to Al0.30Ga0.70N, and a thickness of 1 nanometer to 5 nanometers.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, wherein the indium aluminum nitride layer has a stoichiometry of In0.16Al0.84N to In0.18Al0.82N and a thickness of 3.5 nanometers to 4.5 nanometers.

### Claim 14 (depends on 7)

The semiconductor device of claim 7, wherein the second AlGaN layer has a stoichiometry of Al0.05Ga0.95N to Al0.30Ga0.70N, and a thickness of 4 nanometers to 20 nanometers.

### Claim 15

A semiconductor device, comprising:
a buffer layer;
a first GaN layer over the buffer layer;
a second GaN layer over the first GaN layer;
a first AlGaN layer disposed over the second GaN layer, the first AlGaN layer having less than 1 atomic percent indium;
an indium aluminum nitride layer over the AlGaN layer;
a second AlGaN layer disposed over the indium aluminum nitride layer;
a gate recess extending through the second AlGaN layer and the indium aluminum nitride layer in an enhancement mode GaN FET, wherein the gate recess does not extend through the first AlGaN layer;
a gate dielectric layer of the enhancement mode GaN FET disposed over the first AlGaN layer in the gate recess;
a gate of the enhancement mode GaN FET disposed over the gate dielectric layer in the gate recess;
a gate dielectric layer of a depletion mode GaN FET disposed over the second AlGaN layer, the indium aluminum nitride layer and the first AlGaN layer; and
a gate of the depletion mode GaN FET disposed over the gate dielectric layer of the depletion mode GaN FET.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the first AlGaN layer has a thickness of 1 nanometer to 5 nanometers.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the indium aluminum nitride layer has a thickness of 3.5 nanometers to 4.5 nanometers.

### Claim at position 18 (depends on 15)

18: The semiconductor device of claim 15, wherein the second AlGaN layer has a thickness of 4 nanometers to 20 nanometers.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein:
the gate dielectric layer of the enhancement mode GaN FET and the gate dielectric layer of the depletion mode GaN FET have substantially equal thicknesses and compositions; and
the gate of the enhancement mode GaN FET and the gate of the depletion mode GaN FET have substantially equal compositions.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the gate dielectric layer of the enhancement mode GaN FET and the gate dielectric layer of the depletion mode GaN FET comprise aluminum oxide.