# US 2021/0242174 A1 · Multi-height interconnect structures and associated systems and methods

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- Number: US 2021/0242174 A1
- Document ID: US20210242174A1
- Status: Published application
- Kind: A1
- Application number: 16/781,707
- Filed: 2020-02-04
- Published: 2021-08-05
- Earliest claimed: 2020-02-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kyle K. Kirby
- Web page: https://patentgrep.com/patent/US20210242174A1

## CPC

- H10W 90/00: Package configurations
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Systems and methods for multi-height interconnect structures for a semiconductor device are provided herein. The multi-height interconnect structure generally includes a primary level semiconductor die having a primary conductive pillar and a secondary conductive pillar, where the primary conductive pillar has a greater height than the secondary conductive pillar. The semiconductor device may further include a substrate electrically coupled to the primary level semiconductor die through the primary conductive pillar and a secondary level semiconductor die electrically coupled to the primary level semiconductor die through the secondary conductive pillar. The multi-height pillars may be formed using a single photoresist mask or multiple photoresist masks. In some configurations, the primary and secondary conductive pillars may be arranged on only the front-side of the dies and/or substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a primary level semiconductor die having a primary conductive pillar and a secondary conductive pillar, the primary conductive pillar having a greater height than the secondary conductive pillar;
a substrate electrically coupled to the primary level semiconductor die by the primary conductive pillar; and
a secondary level semiconductor die electrically coupled to the primary level semiconductor die through the secondary conductive pillar,
wherein the distance between the primary level semiconductor die and the substrate is greater than the distance between the primary level semiconductor die and the secondary level semiconductor die based on the height of the primary and secondary conductive pillars.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a tertiary conductive pillar having a height less than the primary and secondary conductive pillars, wherein the tertiary conductive pillar is electrically coupled to the secondary level semiconductor die.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a tertiary level semiconductor die electrically coupled to the tertiary conductive pillar, wherein the distance between the tertiary level semiconductor die and the secondary level semiconductor die is less than the distance between the primary level semiconductor die and the secondary level semiconductor die.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a second secondary level semiconductor die between the primary level semiconductor die and the tertiary level semiconductor die, the second secondary level semiconductor die having a through-silicon via.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the primary level semiconductor die and the tertiary level semiconductor die are electrically coupled through the second secondary level semiconductor die by the through-silicon via.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the second secondary level semiconductor die further comprises a secondary conductive pillar arranged on the backside of the second secondary level semiconductor die for electrically coupling to a component of the semiconductor device.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the primary and secondary conductive pillars are arranged on a front-side of the primary level semiconductor die.

### Claim 8 (depends on 2)

The semiconductor device of claim 2, wherein the secondary and tertiary conductive pillars are arranged on a front-side of the secondary level semiconductor die.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the substrate is electrically coupled to a printed circuit board through a solder ball.

### Claim 10

A method for forming multi-height conductive pillars on a semiconductor die, the method comprising:
applying a first photoresist mask to a surface of the semiconductor die, the photoresist mask having a first resist opening configured to partially form a primary conductive pillar and a second resist opening configured to form a secondary conductive pillar;
electrochemically plating metal by an electrochemical plating process onto the semiconductor die through the first resist opening to partially form the primary conductive pillar to a first height and through the second resist opening to form the secondary conductive pillar to the first height;
removing the first photoresist mask from the semiconductor die to expose the partial primary conductive pillar and the secondary conductive pillar;
applying a second photoresist mask to the surface of the semiconductor die covering the secondary conductive pillar, the photoresist mask having a third resist opening aligned with the partial primary pillar and configured to partially form the primary conductive pillar;
electrochemically plating metal by an electrochemical plating process onto the semiconductor die through the third resist opening to partially form the primary conductive pillar to a second height greater than the first height; and
removing the second photoresist mask from the semiconductor die to expose the primary conductive pillar extending to the second height and the secondary conductive pillar extending to the first height.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first resist opening and the second resist opening have equal diameters.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the first photoresist mask further comprises a fourth resist opening configured to form a tertiary conductive pillar; and
the method further comprises electrochemically plating metal by an electrochemical plating process onto the semiconductor die through the fourth resist opening to form the tertiary conductive pillar to a third height less than the first and second heights.

### Claim 13 (depends on 12)

The method of claim 12, wherein the fourth resist opening has a smaller diameter than the first and second resist openings.

### Claim 14

A method of making a semiconductor assembly with multi-height conductive pillars, comprising:
applying a first photoresist mask to a surface of a first semiconductor die, the photoresist mask having a first resist opening configured to form a primary conductive pillar and a second resist opening configured to form a secondary conductive pillar;
electrochemically plating metal by an electrochemical plating process onto the first semiconductor die through the first resist opening to form the primary conductive pillar to a first height and through the second resist opening to form the secondary conductive pillar to a second height;
removing the first photoresist mask from the first semiconductor die to expose the partial primary conductive pillar and the secondary conductive pillar;
electrically coupling the first semiconductor die to a substrate via the primary pillars; and
electrically coupling the first semiconductor die to a second semiconductor die via the secondary pillars.

### Claim 15 (depends on 14)

The method of claim 14, wherein a diameter of the second resist opening is smaller than a diameter of the first resist opening such that the second height is less than the first height.

### Claim 16 (depends on 14)

The method of claim 14, wherein, prior to electrically coupling the first semiconductor to the substrate, the method further comprises:
applying a second photoresist mask to the surface of the first semiconductor die covering the secondary conductive pillar, the photoresist mask having a third resist opening aligned with the primary pillar and configured to further form the primary conductive pillar;
electrochemically plating metal by an electrochemical plating process onto the first semiconductor die through the third resist opening to further form the primary conductive pillar to a third height greater than the second height; and
removing the second photoresist mask from the semiconductor die to expose the primary conductive pillar extending to the third height and the secondary conductive pillar extending to the second height.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the first photoresist mask further comprises a fourth resist opening configured to form a tertiary conductive pillar; and prior to applying a second photoresist mask to the surface of the first semiconductor die,
the method further comprises electrochemically plating metal by an electrochemical plating process onto the first semiconductor die through the fourth resist opening to form the tertiary conductive pillar to a fourth height less than the second and third heights.

### Claim 18 (depends on 17)

The method of claim 17, further comprising electrically coupling the first semiconductor die to a third semiconductor die via the tertiary pillars.

### Claim 19 (depends on 17)

The method of claim 17, wherein the fourth resist opening has a smaller diameter than the second resist opening.