# US 2021/0242171 A1 · Semiconductor package and method for fabricating the same

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- Number: US 2021/0242171 A1
- Document ID: US20210242171A1
- Status: Published application
- Kind: A1
- Application number: 17/036,465
- Filed: 2020-09-29
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: SEONG GWAN LEE
- Web page: https://patentgrep.com/patent/US20210242171A1

## CPC

- H10W 90/00: Package configurations
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 2207/105: Aspects related to pads, pins or terminals
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/01: {Manufacture or treatment}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor package is provided. The semiconductor package includes: a substrate; a first buffer chip and a second buffer chip located on an upper part of the substrate; a plurality of nonvolatile memory chips located on the upper part of the substrate and including a first nonvolatile memory chip and a second nonvolatile memory chip, the first nonvolatile memory chip being electrically connected to the first buffer chip, and the second nonvolatile memory chip being electrically connected to the second buffer chip; a plurality of external connection terminals connected to a lower part of the substrate; and a rewiring pattern located inside the substrate. The rewiring pattern is configured to diverge an external electric signal received through one of the plurality of external connection terminals into first and second signals, transmit the first signal to the first buffer chip, and transmit the second signal to the second buffer chip.

## Claims

### Claim 1

A semiconductor package comprising:
a substrate;
a first buffer chip and a second buffer chip located on an upper part of the substrate;
a plurality of nonvolatile memory chips located on the upper part of the substrate and including a first nonvolatile memory chip and a second nonvolatile memory chip, the first nonvolatile memory chip being electrically connected to the first buffer chip, and the second nonvolatile memory chip being electrically connected to the second buffer chip;
a plurality of external connection terminals connected to a lower part of the substrate; and
a rewiring pattern located inside the substrate, the rewiring pattern configured to diverge an external electric signal received through one of the plurality of external connection terminals into first and second signals, transmit the first signal to the first buffer chip and transmit the second signal to the second buffer chip.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, further comprising:
a diverging chip,
wherein the diverging chip receives the external electric signal from the one external connection terminal, and transmits the received external electric signal to the rewiring pattern.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the diverging chip is located on the upper part of the substrate.

### Claim 4 (depends on 2)

The semiconductor package of claim 2, wherein the diverging chip is located inside the substrate.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the external electric signal is diverged into the first and second signals at a diverging point in the rewiring pattern,
the first buffer chip and the second buffer chip are spaced apart from each other in a first direction, and
the diverging point is located at a center of the rewiring pattern in the first direction.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, further comprising:
a controller,
wherein the external electric signal is a control signal received from the controller.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein the rewiring pattern comprises:
a first vertical rewiring pattern and a first horizontal rewiring pattern configured to transmit the first signal to the first buffer chip, and
a second vertical rewiring pattern and a second horizontal rewiring pattern configured to transmit the second signal to the second buffer chip,
the first vertical rewiring pattern and the second vertical rewiring pattern extend in the first direction,
the first horizontal rewiring pattern and the second horizontal rewiring pattern extend in a second direction perpendicular to the first direction, and
the first horizontal rewiring pattern is lower than the second horizontal rewiring pattern in the first direction.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein the rewiring pattern comprises a third vertical rewiring pattern including a first end connected to the one external connection terminal and extending in the first direction, and
the electric signal is diverged at a second other end of the third vertical rewiring pattern.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the first buffer chip and the second buffer chip are connected to the rewiring pattern in a form of a flip-chip.

### Claim 10

A semiconductor package comprising:
a controller which transmits a control signal including a first channel signal and a second channel signal; and
a first nonvolatile memory package which receives the first channel signal, and a second nonvolatile memory package which receives the second channel signal,
wherein the first nonvolatile memory package and the second nonvolatile memory package are located on a single substrate, and
the first channel signal and the second channel signal are diverged from the control signal in the substrate.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein a transmission length of the first channel signal is the same as a transmission length of the second channel.

### Claim 12 (depends on 10)

The semiconductor package of claim 10, further comprising:
a diverging chip,
wherein the diverging chip receives the control signal and diverges the received control signal into the first channel signal and the second channel signal.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the diverging chip is located on an upper part of the substrate.

### Claim 14 (depends on 12)

The semiconductor package of claim 12, wherein the diverging chip is located inside the substrate.

### Claim 15 (depends on 10)

The semiconductor package of claim 10, wherein the first channel signal is transmitted to the first nonvolatile memory package through a first horizontal path and a first vertical path,
the second channel signal is transmitted to the second nonvolatile memory package through a second horizontal path and a second vertical path,
the first vertical path and the second vertical path extend in a first direction,
the first horizontal path and the second horizontal path extend in a second direction perpendicular to the first direction, and
the first horizontal path is lower than the second horizontal path in the first direction.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the control signal is transmitted through a third vertical path extending in the first direction before being diverged.

### Claim 17 (depends on 10)

The semiconductor package of claim 10, wherein the substrate includes a first layer and a second layer located at different heights from each other in the first direction perpendicular to the substrate,
the first channel signal and the second channel signal are transmitted through both the first layer and the second layer, and
a transmission length of the first channel signal transmitted through the first layer is longer than a transmission length of the second channel signal transmitted through the first layer.

### Claim 18

A semiconductor package comprising:
a substrate;
a first buffer pad and a second buffer pad located on an upper part of the substrate;
a first buffer chip and a second buffer chip electrically connected to each of the first buffer pad and the second buffer pad;
a plurality of nonvolatile memory chips located on the upper part of the substrate and including a first nonvolatile memory chip and a second nonvolatile memory chip, the first nonvolatile memory chip being electrically connected to the first buffer chip, and the second nonvolatile memory chip being electrically connected to the second buffer chip;
a plurality of external connection terminals connected to a lower part of the substrate;
a controller which transmits a control signal including a first channel signal and a second channel signal to one of the plurality of external connection terminals; and
a rewiring pattern which is located inside the substrate, diverges the control signal into the first and second channel signals, transmits the first channel signal to the first buffer chip, and transmits the second channel signal to the second buffer chip.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, wherein the rewiring pattern comprises:
a first vertical rewiring pattern and a first horizontal rewiring pattern in which the first channel signal is transmitted to the first buffer chip,
a second vertical rewiring pattern and a second horizontal rewiring pattern in which the second channel signal is transmitted to the second buffer chip,
the first vertical rewiring pattern and the second vertical rewiring pattern extend in a first direction,
the first horizontal rewiring pattern and the second horizontal rewiring pattern extend in a second direction perpendicular to the first direction, and
the first horizontal rewiring pattern is lower than the second horizontal rewiring pattern in the first direction.

### Claim 20 (depends on 19)

The semiconductor package of claim 19, wherein the rewiring pattern further comprises a third vertical rewiring pattern including a first end connected to the one external connection terminal at one end and extends in the first direction, and
the control signal is diverged at a second other end of the third vertical rewiring pattern.

### Claim at position 21

21-26. (canceled)