# US 2021/0242169 A1 · Encapsulated fan-in semiconductor package with heat spreader and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242169 A1 - Document ID: US20210242169A1 - Status: Published application - Kind: A1 - Application number: 16/971,412 - Filed: 2019-02-25 - Published: 2021-08-05 - Earliest claimed: 2018-02-23 - Assignees: Chengdu Eswin Sip Technology Co., Ltd. - Applicants: Chengdu Eswin Sip Technology Co., Ltd. - Inventors: Minghao SHEN; Xiaotian ZHOU - Web page: https://patentgrep.com/patent/US20210242169A1 ## CPC - H10W 72/0198: {batch processes} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 72/072: {of bump connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed is a method of manufacturing a semiconductor device that includes securing a lower surface of a wafer to a supporting surface of a carrier substrate formed of copper or other metal having good thermal conductance. Further semiconductor processing for packaging can include forming an RDL on the wafer, etching scribe channels through the wafer, and coating the wafer with encapsulant. After dicing, the metal carrier remains in contact with and supporting the lower surface of the wafer, and the remainder of the wafer remains coated by the encapsulant. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, comprising: providing a wafer having a plurality of integrated circuits; securing a lower surface of the wafer to a supporting surface of a carrier substrate; forming a redistribution layer (RDL) on an upper surface of the wafer, the upper surface of the wafer being opposite the lower surface of the wafer; etching scribe channels through the RDL and at least a portion of the wafer towards the carrier substrate in the wafer from the RDL, to the carrier substrate; encapsulating the wafer and RDL, within an encapsulant, including providing a portion of the encapsulant in the scribe channels; and dicing the wafer and carrier substrate along the scribe channels without exposing the wafer such that the wafer remains covered on a first portion thereof by the carrier substrate and a remaining portion thereof by the encapsulant. ### Claim 2 (depends on 1) The method of claim 1, wherein the plurality of integrated circuits includes at least two identical integrated circuits. ### Claim 3 (depends on 1) The method of claim 1, wherein the securing of the lower surface of the wafer to the supporting surface of the carrier substrate includes forming a bonding surface on at least one of the carrier substrate and the wafer. ### Claim 4 (depends on 3) The method of claim 3, wherein the forming of the bonding surface includes planarizing chieve a bonding surface having a roughness of less than or equal to 20 Angstroms. ### Claim 5 (depends on 1) The method of claim 1, wherein the securing of the lower surface of the wafer to the supporting surface of the carrier substrate includes coating the supporting surface of the carrier substrate with a corrosion inhibitor. ### Claim 6 (depends on 5) The method of claim 5, wherein the securing of the lower surface of the wafer to the supporting surface of the carrier substrate further includes bonding lower surface of the wafer to the supporting surface of the carrier substrate by proximity contact. ### Claim 7 (depends on 6) The method of claim 6, wherein the proximity contact is made with a bonding force that is less than or equal to 100 g/mm2. ### Claim 8 (depends on 1) The method of claim 1, wherein the securing of the lower surface of the wafer to the supporting surface of the carrier substrate includes coating at least one of the lower surface and the supporting surface with a metal layer. ### Claim 9 (depends on 8) The method of claim 8, wherein the metal layer includes at least one of titanium, tantalum, and copper. ### Claim 10 (depends on 8) The method of claim 8, wherein the metal layer is less than or equal to 1 nm in thickness. ### Claim 11 (depends on 8) The method of claim 8, wherein the securing of the lower surface of the wafer to the supporting surface of the carrier substrate further includes bonding lower surface of the wafer to the supporting surface of the carrier substrate by proximity contact. ### Claim 12 (depends on 11) The method of claim 11, wherein the proximity contact is made with a bonding force that is less than or equal to 100 g/mm2. ### Claim 13 (depends on 1) The method of claim 1, wherein the securing of the lower surface of the wafer to the supporting surface of the carrier substrate includes a self-annealing process resulting bonding between the lower surface of the wafer and the supporting surface of the carrier substrate. ### Claim 14 (depends on 13) The method of claim 13, wherein the self-annealing process results in ionic bonding between the lower surface of the wafer and the supporting surface of the carrier substrate. ### Claim 15 (depends on 13) The method of claim 13, wherein the self-annealing process is performed at a temperature in a range of 15C to 27C. ### Claim 16 (depends on 1) The method of claim 1, wherein the securing of the lower surface of the wafer to the supporting surface of the carrier substrate includes an annealing process performed at a designated temperature. ### Claim 17 (depends on 16) The method of claim 16, wherein the self-annealing process is performed at a designated in a range of 15C to 250C. ### Claim 18 (depends on 1) The method of claim 1, wherein the first portion of the wafer that remains covered by the carrier substrate is the lower surface of the waver. ### Claim 19 (depends on 1) The method of claim 1, wherein the remaining portion of the wafer that remains covered by the carrier substrate includes the upper surface and side surfaces of the wafer. ### Claim 20 An integrated circuit package, comprising: a semiconductor wafer having an integrated circuit formed therein; an RUL formed on an upper surface of the wafer; a carrier substrate having a metal upper surface bonded to a lower surface of the semiconductor wafer by ionic bonding; and an encapsulant coating at least a portion of the sides and upper surface of the wafer.