# US 2021/0242167 A1 · Semiconductor packages using package in package systems and related methods

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- Number: US 2021/0242167 A1
- Document ID: US20210242167A1
- Status: Published application
- Kind: A1
- Application number: 17/158,143
- Filed: 2021-01-26
- Published: 2021-08-05
- Earliest claimed: 2020-02-04
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Inpil YOO; Maria Cristina ESTACIO; Jerome TEYSSEYRE; Seungwon IM; JooYang EOM
- Web page: https://patentgrep.com/patent/US20210242167A1

## CPC

- H10W 90/811: {Multiple chips on leadframes}
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10W 70/466: {Tape carriers or flat leads}
- H10W 70/467: {Multilayered additional interconnections}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/01: {Manufacture or treatment}
- H10W 74/01: Manufacture or treatment
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6523: {for connecting to pads at different heights at the same side of the package substrate, interposer or RDL}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07354: {changes in dispositions}
- H10W 72/076: {of strap connectors}
- H10W 72/07631: {Techniques}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/634: {Cross-sectional shape}
- H10W 72/647: {Dispositions of multiple strap connectors}
- H10W 72/853: {On the same surface}
- H10W 72/868: {Die-attach connectors and strap connectors}
- H10W 72/874: {On different surfaces}
- H10W 72/886: {Die-attach connectors and strap connectors}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/00: Package configurations
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/763: {between laterally-adjacent chips}
- H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

## Claims

### Claim 1

A semiconductor package comprising:
two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes;
a first interconnect layer coupled at a source of each of the two more die;
a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and
an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

### Claim 2 (depends on 1)

The package of claim 1, wherein the encapsulant encapsulates a portion of the gate package contact.

### Claim 3 (depends on 1)

The package of claim 1, wherein each metal layer and the gate package contact are configured to couple with a substrate.

### Claim 4 (depends on 1)

The package of claim 1, wherein the first interconnect layer is configured to couple with a clip and electrically coupled with a substrate through the clip.

### Claim 5 (depends on 1)

The package of claim 1, wherein the second interconnect layer is configured to couple with a clip.

### Claim 6 (depends on 1)

The package of claim 1, wherein the two or more die are power semiconductor die.

### Claim 7 (depends on 1)

The package of claim 1, wherein the two or more die comprise silicon carbide.

### Claim 8 (depends on 1)

The package of claim 1, further comprising a leadframe where the first interconnect layer, the second interconnect layer, each metal layer, and the gate package contact are comprised in the leadframe.

### Claim 9

A semiconductor package comprising:
two or more encapsulated die assemblies, each encapsulated die assembly comprising:
two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die;
a first interconnect layer coupled at a source of each of the two more die;
a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and
an encapsulant surrounding the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer;
one of a substrate or a leadframe coupled to the two or more encapsulated die assemblies; and
two or more clips coupled to a source side of the two or more encapsulated die assemblies.

### Claim 10 (depends on 9)

The package of claim 9, wherein the one of the substrate or the leadframe is coupled to the two or more encapsulated die assemblies at a drain side of the two or more encapsulated die assemblies.

### Claim 11 (depends on 9)

The package of claim 9, wherein at least three die are electrically coupled in parallel in each of the two or more encapsulated die assemblies.

### Claim 12 (depends on 9)

The package of claim 9, further comprising two or more leads coupled to the one of the substrate or the leadframe.

### Claim 13 (depends on 9)

The package of claim 9, further comprising one or more clips coupled to the one of the substrate or the leadframe.

### Claim 14 (depends on 9)

The package of claim 9, further comprising an encapsulant surrounding the two or more encapsulated die assemblies and at least a portion of the one of the substrate or the leadframe.

### Claim 15 (depends on 9)

The package of claim 9, wherein the two or more encapsulated die assemblies further comprise a leadframe.

### Claim 16

A method of forming a semiconductor package, the method comprising:
forming one or more die assemblies by:
providing two or more die;
coupling each of the two or more die to a metal layer at a drain of each of the two or more die;
forming a first interconnect layer coupled to a source of each of the two or more die;
encapsulating the two or more die with an encapsulant, at least a portion of the first interconnect layer, and at least a portion of each metal layer using one of a transfer molding or laminating process; and
forming a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact using one of a clip or one or more vias; and
coupling the one or more die assemblies to one of a substrate or a leadframe.

### Claim 17 (depends on 16)

The method of claim 16, further comprising coupling two or more clips to a source side of the two or more encapsulated die assemblies.

### Claim 18 (depends on 16)

The method of claim 16, wherein coupling each of the two or more die to the metal layer further comprises using a silver sintering film and pressure sintering.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming one or more die assemblies further comprises grinding the encapsulant to expose at least the portion of the first interconnect layer and at least the portion of each metal layer.

### Claim 20 (depends on 16)

The method of claim 16, wherein forming one or more die assemblies further comprises forming one or more vias in the encapsulant using a laser and filling the one or more vias with copper through electroplating.