# US 2021/0242164 A1 · Resist structure for forming bumps > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242164 A1 - Document ID: US20210242164A1 - Status: Published application - Kind: A1 - Application number: 16/777,416 - Filed: 2020-01-30 - Published: 2021-08-05 - Earliest claimed: 2020-01-30 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Eiji Nakamura; Toyohiro Aoki; Takashi Hisada; Risa Miyazawa - Web page: https://patentgrep.com/patent/US20210242164A1 ## CPC - H10W 72/072: {of bump connectors} - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/073: {of die-attach connectors} - H10W 72/30: Die-attach connectors - H10W 90/00: Package configurations - H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing} - H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01251: {Changing the shapes of bumps} - H10W 72/01255: {by using masks} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01955: {by using masks} - H10W 72/07236: {Soldering or alloying} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities. ## Claims ### Claim 1 A method for fabricating a resist structure, the method comprising: forming two or more conductive pads on a substrate; forming a lower resist on the substrate and two or more lower pads; patterning the lower resist to form a lower cavity overlapping each of the two or more conductive pads, wherein each of the two or more lower cavities has a first diameter; forming an upper resist on the lower resist; and patterning the upper resist to form an upper cavity overlapping the two or more lower cavities, wherein the upper cavity has cavity regions having a second diameter larger than the first diameter above each of the two or more lower cavities, and connecting regions between adjacent cavity regions. ### Claim 2 (depends on 1) The method of claim 1, wherein at least three cavity regions are connected by connecting regions. ### Claim 3 A method for fabricating a semiconductor device, the method comprising: forming a plurality of conductive pads on a substrate; patterning a lower resist to form a plurality of lower cavities, wherein each of the plurality of lower cavities is located above a corresponding one of the plurality of conductive pads; patterning an upper resist to form an upper cavity overlapping the plurality of lower cavities, wherein the upper cavity has a plurality of cavity regions, wherein each of the cavity regions is located above a corresponding one of the plurality of lower cavities, and each cavity region has a diameter larger than a diameter of the corresponding one of the plurality of lower cavities, and a connecting region between adjacent cavity regions; forming a conductive pillar in each of the plurality of lower cavities; filling conductive material in the plurality of cavity regions and connecting regions to form a plurality of bumps, each of the plurality of bumps being located on a corresponding one of the plurality of conductive pillars; and connecting the plurality of bumps to a circuit board by flip-chip bonding. ### Claim 4 (depends on 3) The method of claim 3, further comprising depositing the upper resist on the lower resist after forming the plurality of conductive pillars. ### Claim 5 (depends on 4) The method of claim 4, further comprising planarizing a surface of a layer including the lower resist and the plurality of conductive pillars after forming the plurality of conductive pillars and before depositing the upper resist on the lower resist. ### Claim 6 (depends on 3) The method of claim 3, further comprising depositing the upper resist on the lower resist before forming the plurality of conductive pillars. ### Claim 7 (depends on 3) The method of claim 3, wherein the plurality of conductive pillars are formed by electrolytic plating. ### Claim 8 (depends on 7) The method of claim 7, further comprising: depositing a seed layer on the substrate; and depositing the lower resist on the seed layer, wherein the plurality of bumps are connected to the circuit board after the upper resist and the lower resist are removed and parts of the seed layer are etched. ### Claim 9 (depends on 3) The method of claim 3, wherein the plurality of conductive pillars are formed by electroless plating. ### Claim 10 (depends on 9) The method of claim 9, further comprising depositing the lower resist on the substrate, wherein the plurality of bumps are connected to the circuit board along with the upper resist and the lower resist. ### Claim 11 (depends on 3) The method of claim 3, wherein the conductive material is molten solder injected using Injection Molded Solder (IMS) technology. ### Claim 12 (depends on 11) The method of claim 11, wherein at least three cavity regions are connected by connecting regions. ### Claim 13 (depends on 12) The method of claim 12, wherein the molten solder is filled in the at least three cavity regions by an injection head scanning in a direction, the injection head being a head for injecting the molten solder, the direction being perpendicular to a direction in which the at least three cavity regions are aligned. ### Claim 14 (depends on 3) The method of claim 3, wherein the conductive material is plated solder. ### Claim 15 A resist structure comprising: a plurality of conductive pads on a substrate; a lower resist having a plurality of lower cavities, the lower resist being on the substrate, and each of the plurality of lower cavities being located above a corresponding one of the plurality of conductive pads; and an upper resist on the lower resist, wherein the upper resist has an upper cavity with a plurality of cavity regions, each of the plurality of cavity regions overlapping an associated lower cavity, and connecting regions between adjacent cavity regions, wherein the cavity regions have a diameter larger than a diameter of each of the plurality of lower cavities. ### Claim 16 (depends on 15) The resist structure of claim 15, wherein at least three cavity regions are connected by connecting regions. ### Claim 17 A semiconductor device comprising: a plurality of conductive pads on a substrate; a lower resist having a plurality of lower cavities, wherein each of the plurality of lower cavities overlaps a corresponding one of the plurality of conductive pads; an upper resist on the lower resist, wherein the upper resist has an upper cavity with a plurality of cavity regions, each of the plurality of cavity regions overlapping an associated lower cavity, and connecting regions between adjacent cavity regions, wherein the cavity regions have a diameter larger than a diameter of the corresponding one of the plurality of lower cavities; a plurality of conductive pillars, each of the plurality of conductive pillars being located in the corresponding one of the plurality of lower cavities; a plurality of bumps of conductive material in the plurality of cavity regions and connecting regions, each of the plurality of bumps being located on a corresponding one of the plurality of conductive pillars; and a circuit board to which the plurality of bumps are connected by flip-chip bonding. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the conductive material is molten solder injected using Injection Molded Solder (IMS) technology. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein at least four cavity regions are connected by connecting regions. ### Claim 20 (depends on 17) The semiconductor device of claim 17, wherein the conductive material is plated solder. ### Claim 21 An electronic apparatus comprising: a semiconductor device; and a signal processor configured to process a signal outputted from the semiconductor device, wherein the semiconductor device comprises: a plurality of conductive pads on a substrate; a lower resist having a plurality of lower cavities, wherein each of the plurality of lower cavities overlaps a corresponding one of the plurality of conductive pads; an upper resist on the lower resist, wherein the upper resist has an upper cavity with a plurality of cavity regions, each of the plurality of cavity regions overlapping an associated lower cavity, and connecting regions between adjacent cavity regions, wherein the cavity regions have a diameter larger than a diameter of the corresponding one of the plurality of lower cavities; a plurality of conductive pillars, each of the plurality of conductive pillars being located in the corresponding one of the plurality of lower cavities; a plurality of bumps of conductive material in the plurality of cavity regions and connecting regions, each of the plurality of bumps being located on a corresponding one of the plurality of conductive pillars; and a circuit board to which the plurality of bumps are connected by flip-chip bonding. ### Claim 22 (depends on 21) The electronic apparatus of claim 21, wherein the conductive material is molten solder injected using Injection Molded Solder (IMS) technology. ### Claim 23 (depends on 22) The electronic apparatus of claim 22, wherein at least three cavity regions are connected by connecting regions. ### Claim 24 (depends on 21) The electronic apparatus of claim 21, wherein the conductive material is plated solder.