# US 2021/0242163 A1 · Semiconductor arrangement and method for producing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242163 A1 - Document ID: US20210242163A1 - Status: Published application - Kind: A1 - Application number: 17/160,643 - Filed: 2021-01-28 - Published: 2021-08-05 - Earliest claimed: 2020-02-03 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Frank Sauerland - Web page: https://patentgrep.com/patent/US20210242163A1 ## CPC - H10W 72/075: {of bond wires} - H10W 90/00: Package configurations - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W 76/15: Containers comprising an insulating or insulated base - H10W 76/47: Solid or gel fillings - H10W 72/073: {of die-attach connectors} - H10W 72/07331: {Connecting techniques} - H10W 72/07336: {Soldering or alloying} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07553: {changes in shapes} - H10W 72/07554: {changes in dispositions} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/531: {Shapes of wire connectors} - H10W 72/534: {being rectangular} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/537: {Multiple bond wires having different shapes} - H10W 72/5438: {the bond wires having multiple connections on the same bond pad} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 76/10: Containers or parts thereof - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor arrangement includes a controllable semiconductor element having an active region, and bonding wires arranged in parallel to each other in a first horizontal direction. The active region has a first length in the first horizontal direction and a first width in a second horizontal direction perpendicular to the first horizontal direction. Each bonding wire is electrically and mechanically coupled to the controllable semiconductor element by a first number of bond connections arranged above the active region. A first bond connection of each bonding wire is arranged at a first distance from a first edge of the active region. A second bond connection of each bonding wire is arranged at a second distance from a second edge of the active region opposite the first edge. The first and second distances are both less than the first length divided by twice the first number of bond connections. ## Claims ### Claim 1 A semiconductor arrangement, comprising: a controllable semiconductor element comprising an active region; and a plurality of bonding wires arranged in parallel to each other in a first horizontal direction, wherein the active region has a first length in the first horizontal direction and a first width in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of bonding wires is electrically and mechanically coupled to the controllable semiconductor element by a first number of bond connections, wherein each of the bond connections is arranged above the active region in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, wherein a first bond connection of each of the plurality of bonding wires is arranged at a first distance from a first edge of the active region in the first horizontal direction, wherein the first distance is less than the first length divided by twice the first number of bond connections, wherein the first bond connection of each of the plurality of bonding wires is the bond connection arranged closest to the first edge, wherein a second bond connection of each of the plurality of bonding wires is arranged at a second distance from a second edge of the active region in the first horizontal direction, wherein the second edge is arranged opposite the first edge, wherein the second distance is less than the first length divided by twice the first number of bond connections, wherein the second bond connection of each of the plurality of bonding wires is the bond connection arranged closest to the second edge. ### Claim 2 (depends on 1) The semiconductor arrangement of claim 1, wherein: a first bonding wire of the plurality of bonding wires is arranged closest to a third edge of the active region that is perpendicular to the first and the second edge; a distance between the first bonding wire and the third edge is less than the first width divided by twice the overall number of bonding wires; a second bonding wire of the plurality of bonding wires is arranged closest to a fourth edge of the active region that is opposite the third edge; a distance between the second bonding wire and the fourth edge is less than the first width divided by twice the overall number of bonding wires. ### Claim 3 (depends on 1) The semiconductor arrangement of claim 1, wherein a distance between two neighboring bonding wires is equal for the plurality of bonding wires. ### Claim 4 (depends on 1) The semiconductor arrangement of claim 1, wherein: the plurality of bonding wires is arranged in a first group and a second group; the bonding wires within each of the first and second group are equally spaced from each other; and a distance between the first group of bonding wires and the second group of bonding wires is greater than a distance between the individual bonding wires of each group. ### Claim 5 (depends on 1) The semiconductor arrangement of claim 1, wherein a first end of each of the plurality of bonding wires extends from the respective first bond connection and is mechanically and electronically coupled to a semiconductor substrate. ### Claim 6 (depends on 5) The semiconductor arrangement of claim 5, wherein a second end of each of the plurality of bonding wires extends from the respective second bond connection and is not mechanically or electrically coupled to any other components. ### Claim 7 (depends on 5) The semiconductor arrangement of claim 5, wherein a second end of each of the plurality of bonding wires extends from the respective second bond connection and is mechanically and electrically coupled to the semiconductor substrate, and wherein the second end of each of the plurality of bonding wires is not used to electrically contact the controllable semiconductor element such that an electrical contact is solely provided by the first ends of the plurality of bonding wires. ### Claim 8 (depends on 7) The semiconductor arrangement of claim 7, wherein: the semiconductor substrate comprises a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer; the first metallization layer is a structured layer comprising at least two different sections, recesses are formed between the at least two different sections; the controllable semiconductor element is mounted on the first metallization layer; the first end of each bonding wire is mechanically and electrically coupled to a first section of the first metallization layer; and the second end of each bonding wire is mechanically and electrically coupled to a second section of the first metallization layer different from the first section. ### Claim 9 (depends on 7) The semiconductor arrangement of claim 7, wherein the first end of each of the plurality of bonding wires is electrically coupled to a different electrical potential than the second end of each of the plurality of bonding wires. ### Claim 10 (depends on 6) The semiconductor arrangement of claim 6, wherein a length of the second end of each of the plurality of bonding wires is at least 1 mm, at least 3 mm, or at least 5 mm ### Claim 11 (depends on 1) The semiconductor arrangement of claim 1, wherein the active region of the controllable semiconductor element is a region carrying a current. ### Claim 12 (depends on 11) The semiconductor arrangement of claim 11, wherein the controllable semiconductor element further comprises an edge region surrounding the active region in a horizontal plane, and wherein the edge region of the controllable semiconductor element is a region that does not carry any currents. ### Claim 13 A method for producing a semiconductor arrangement, the method comprising: mounting a plurality of bonding wires on a controllable semiconductor element, the controllable semiconductor element comprising an active region, wherein mounting the plurality of bonding wires on the controllable semiconductor element comprises: for each of the plurality of bonding wires, forming a first number of bond connections between the bonding wire and the controllable semiconductor element, thereby electrically and mechanically coupling the bonding wire to the controllable semiconductor element, wherein: the plurality of bonding wires is arranged in parallel to each other in a first horizontal direction; the active region has a first length in the first horizontal direction and a first width in a second horizontal direction perpendicular to the first horizontal direction; each of the bond connections is arranged above the active region in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction; a first bond connection of each of the plurality of bonding wires is arranged at a first distance from a first edge of the active region in the first horizontal direction, the first distance is less than the first length divided by twice the first number of bond connections, the first bond connection of each of the plurality of bonding wires is the bond connection arranged closest to the first edge, a second bond connection of each of the plurality of bonding wires is arranged at a second distance from a second edge of the active region in the first horizontal direction, the second edge is arranged opposite the first edge, the second distance is less than the first length divided by twice the first number of bond connections, the second bond connection of each of the plurality of bonding wires is the bond connection arranged closest to the second edge.