# US 2021/0242101 A1 · Semiconductor packages having a dam structure

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- Number: US 2021/0242101 A1
- Document ID: US20210242101A1
- Status: Published application
- Kind: A1
- Application number: 16/928,159
- Filed: 2020-07-14
- Published: 2021-08-05
- Earliest claimed: 2020-02-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dongho KIM; Jongbo SHIM; Hwanpil PARK; Jangwoo LEE
- Web page: https://patentgrep.com/patent/US20210242101A1

## CPC

- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/30: Die-attach connectors
- H10W 72/50: Bond wires
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 72/01308: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/075: {of bond wires}
- H10W 72/07523: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/354: {comprising polymers}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

## Claims

### Claim 1

A semiconductor package comprising:
a substrate having bonding pads at an upper surface thereof;
a lower semiconductor chip disposed on the substrate and at least one upper semiconductor chip disposed on the lower semiconductor chip;
a dam structure disposed on the substrate and having a closed loop shape surrounding the lower semiconductor chip, the dam structure including narrow and wide dams, the narrow dam being disposed between the lower semiconductor chip and the bonding pads, and the wide dam having a greater inner width than the narrow dam; and
an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

### Claim 2 (depends on 1)

The semiconductor package according to claim 1, wherein a distance between the lower semiconductor chip and the wide dam is greater than a distance between the lower semiconductor chip and the narrow dam.

### Claim 3 (depends on 1)

The semiconductor package according to claim 1, wherein a distance between the lower semiconductor chip and the narrow dam is smaller than a distance between the lower semiconductor chip and each of the bonding pads.

### Claim 4 (depends on 1)

The semiconductor package according to claim 1, wherein:
the lower semiconductor chip is electrically connected to the substrate through bumps; and
the upper semiconductor chip is electrically connected to the substrate through bonding wires.

### Claim 5 (depends on 1)

The semiconductor package according to claim 1, wherein, when viewed in a plan view:
the narrow dam surrounds first to third side surfaces of the lower semiconductor chip;
the wide dam surrounds the first and third surfaces of the lower semiconductor chip and a fourth surface of the lower semiconductor chip;
the dam structure further includes a first connector connecting a first end of the narrow dam and a first end of the wide dam; and
the dam structure further includes a second connector connecting a second end of the narrow dam and a second end of the wide dam.

### Claim 6 (depends on 5)

The semiconductor package according to claim 5, wherein a distance between each of the first and second connectors and a bonding pad disposed adjacent thereto is 50 to 150 μm.

### Claim 7 (depends on 5)

The semiconductor package according to claim 5, wherein the bonding pads are disposed to face corresponding ones of the first to third side surfaces of the lower semiconductor chip.

### Claim 8 (depends on 1)

The semiconductor package according to claim 1, wherein a distance between the narrow dam and each of the bonding pads is 50 to 150 μm.

### Claim 9 (depends on 1)

The semiconductor package according to claim 1, wherein a distance between the wide dam and each adjacent side surface of the substrate is 100 to 300 μm.

### Claim 10 (depends on 1)

The semiconductor package according to claim 1, wherein a distance between the lower semiconductor chip and the narrow dam is 200 to 400 μm.

### Claim 11 (depends on 1)

The semiconductor package according to claim 1, wherein a distance between the lower semiconductor chip and the wide dam is 500 to 1,000 μm.

### Claim 12 (depends on 1)

The semiconductor package according to claim 1, wherein the dam structure has a height of 18 μm or less.

### Claim 13 (depends on 1)

The semiconductor package according to claim 1, further comprising:
an alignment mark disposed on the substrate,
wherein the dam structure includes a cut-out bent at a right angle to face the alignment mark.

### Claim 14 (depends on 1)

The semiconductor package according to claim 1, wherein:
the at least one upper semiconductor chip includes a first upper semiconductor chip and a second upper semiconductor chip; and
the narrow dam includes a first narrow dam disposed between the first upper semiconductor chip and first bonding pads of the bonding pads, and a second narrow dam disposed between the second upper semiconductor chip and second bonding pads of the bonding pads, and the wide dam is disposed between the first narrow dam and the second narrow dam.

### Claim 15

A semiconductor package comprising:
a substrate having bonding pads at an upper surface thereof;
a lower semiconductor chip disposed on the substrate and at least one upper semiconductor chip disposed on the lower semiconductor chip;
an underfill filled between the substrate and the lower semiconductor chip, the underfill including a non-extension portion disposed between the lower semiconductor chip and the bonding pads, and an extension portion having a greater width than the non-extension portion; and
a dam structure disposed on the substrate and having a closed loop shape surrounding the underfill.

### Claim 16 (depends on 15)

The semiconductor package according to claim 15, wherein a distance between the lower semiconductor chip and a side surface of the extension portion is greater than a distance between the lower semiconductor chip and a side surface of the non-extension portion.

### Claim 17 (depends on 15)

The semiconductor package according to claim 15, wherein:
the dam structure includes narrow and wide dams, the narrow dam being disposed between the lower semiconductor chip and the bonding pads, and the wide dam having a greater inner width than the narrow dam;
the narrow dam surrounds the non-extension portion; and
the wide dam surrounds the extension portion.

### Claim 18 (depends on 15)

The semiconductor package according to claim 15, wherein the extension portion and the non-extension portion contact an inner surface of the dam structure.

### Claim 19 (depends on 15)

The semiconductor package according to claim 15, wherein the dam structure spatially separates the underfill from the bonding pads.

### Claim 20

A semiconductor package comprising:
a substrate having bonding pads at an upper surface thereof;
a lower semiconductor chip mounted on the substrate by flip-chip bonding and an upper semiconductor chip mounted on the lower semiconductor chip by wire bonding;
an external connection terminal disposed below the substrate;
a dam structure disposed on the substrate and having a closed loop shape surrounding the lower semiconductor chip, the dam structure including narrow and wide dams, the narrow dam being disposed between the lower semiconductor chip and the bonding pads, and the wide dam having a greater inner width than the narrow dam;
an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip; and
an encapsulant covering the substrate, the lower semiconductor chip, and the upper semiconductor chip.