# US 2021/0242100 A1 · Semiconductor package and manufacturing method thereof

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- Number: US 2021/0242100 A1
- Document ID: US20210242100A1
- Status: Published application
- Kind: A1
- Application number: 16/869,596
- Filed: 2020-05-08
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hao-Cheng Hou; Chien-Hsun Lee; Chung-Shi Liu; Jung-Wei Cheng; Tsung-Ding Wang; Yi-Yang Lei
- Web page: https://patentgrep.com/patent/US20210242100A1

## CPC

- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/473: {containing a filler}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W 90/00: Package configurations
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.

## Claims

### Claim 1

A semiconductor package, comprising:
semiconductor dies;
an encapsulant, encapsulating the semiconductor dies, wherein the encapsulant is made of a first material;
a high-modulus dielectric layer, extending on the encapsulant and the semiconductor dies, wherein the high-modulus dielectric layer is made of a second material; and
a redistribution structure, extending on the high-modulus dielectric layer, wherein the redistribution structure includes redistribution conductive layers embedded in at least a pair of dielectric layers, and the pair of dielectric layers is made of a third material,
wherein an elastic modulus of the first material is higher than an elastic modulus of the third material, and an elastic modulus of the second material is higher than an elastic modulus of the third material.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein a ratio of the elastic modulus of the second material to the elastic modulus of the first material is in the range from 0.5 to 3.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein
at least one semiconductor die of the semiconductor dies comprises an active surface exposing conductive posts embedded in a protective layer,
the high-modulus dielectric layer is disposed on the protective layer,
the protective layer is made of a fourth material, and
a ratio of the elastic modulus of the second material to an elastic modulus of the fourth material is at least 1.5.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the semiconductor dies are electrically connected to the redistribution structure by through vias extending through the high-modulus dielectric layer.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the first material is different from the second material.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein the first material includes an organic resin with first inorganic fillers and the second material includes another organic resin with second inorganic fillers.

### Claim 7 (depends on 5)

The semiconductor package of claim 5, wherein the second material includes a ceramic material.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the encapsulant includes a first portion of a first thickness and a second portion of a second thickness, the second thickness is smaller than the first thickness, and the second portion is disposed between one semiconductor die of the semiconductor dies and the high-modulus dielectric layer.

### Claim 9

A semiconductor package, comprising:
a first semiconductor die;
a second semiconductor die;
an encapsulant, laterally encapsulating the first semiconductor die and the second semiconductor die;
a redistribution structure, disposed over a top surface of the encapsulant, electrically connected to the first semiconductor die and the second semiconductor die;
connective terminals, disposed on an opposite side of the redistribution structure with respect to the first semiconductor die and the second semiconductor die; and
a buffer layer, disposed between the encapsulated first semiconductor die and second semiconductor die on one side and the redistribution structure on an opposite side, the buffer layer comprising:
a high-modulus dielectric layer; and
through vias extending through the high-modulus dielectric layer and electrically connecting the first semiconductor die and the second semiconductor die to the redistribution structure,
wherein a ratio of an elastic modulus of the high-modulus dielectric layer to an elastic modulus of the encapsulant is in a range from 0.5 to 3.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein a portion of the encapsulant extends between the second semiconductor die and the buffer layer.

### Claim 11 (depends on 9)

The semiconductor package of claim 9, wherein a thickness of the buffer layer along a direction normal to the top surface of the encapsulant is in a range from 10 micrometers to 200 micrometers.

### Claim 12 (depends on 9)

The semiconductor package of claim 9, wherein
the first semiconductor die comprises contact posts exposed at an active surface of the first semiconductor die, and
the buffer layer extends on the active surface of the first semiconductor die.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the buffer layer further comprises seed layers interposed between the through vias and the contact posts of the first semiconductor die.

### Claim 14 (depends on 12)

The semiconductor package of claim 12, wherein a width in a first direction of one contact post of the contact posts of the first semiconductor die is substantially equal to a width in the first direction of one through vias of the through vias,
the one through via contacts the one contact post, and
the first direction extends parallel to the active surface of the first semiconductor die.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein the redistribution structure includes a routing trace and a redistribution via connecting the routing trace to the one through via, and the width in the first direction of the one through via is greater than a width in the first direction of the redistribution via.

### Claim 16

A manufacturing method of a semiconductor package, comprising:
encapsulating semiconductor dies in an encapsulant, each semiconductor die having contact posts exposed at a level height of a top surface of the encapsulant;
forming through vias on the contact posts of the encapsulated semiconductor dies;
wrapping the through vias in a high-modulus dielectric layer; and
forming a redistribution structure having a dielectric layer on the high-modulus dielectric layer,
wherein the redistribution structure is electrically connected to the semiconductor dies via the through vias,
an elastic modulus of the dielectric layer is lower than an elastic modulus of the high-modulus dielectric layer, and
an elastic modulus of the high-modulus dielectric layer is about 0.5 to 3 times an elastic modulus of the encapsulant.

### Claim 17 (depends on 16)

The manufacturing method of claim 16, wherein forming the through vias comprises:
disposing a seed material layer over the encapsulated semiconductor dies;
providing an auxiliary mask on the seed material layer, wherein the auxiliary mask includes openings exposing portions of the seed material layer overlying the contact posts of the semiconductor dies; and
disposing a conductive material in the openings of the auxiliary mask.

### Claim 18 (depends on 16)

The manufacturing method of claim 16, wherein wrapping the through vias in a high-modulus dielectric layer comprises:
laminating a high-modulus dielectric material layer on the encapsulated semiconductor dies, the high-modulus dielectric material layer covering the through vias; and
grinding away portions of the high-modulus dielectric material layer until the through vias are exposed to form a high-modulus dielectric layer.

### Claim 19 (depends on 16)

The manufacturing method of claim 16, wherein forming the redistribution structure comprises:
forming the dielectric material layer on the high-modulus dielectric layer, wherein the dielectric material layer has an elastic modulus of in the range of 2 to 4 GPa;
patterning the dielectric material layer to form a dielectric layer having openings exposing the through vias; and
disposing a conductive material within the openings of the dielectric layer to form redistribution conductive layers electrically connected to the through vias.

### Claim 20 (depends on 16)

The manufacturing method of claim 16, wherein encapsulating the semiconductor dies comprises:
placing on a carrier a first semiconductor die and a second semiconductor die, the first semiconductor die and the second semiconductor die differing in thickness so that top surfaces of the contact posts of the first semiconductor die initially reach a higher level height over the carrier than top surfaces of the contact posts of the second semiconductor die;
burying the first semiconductor die and the second semiconductor die in an encapsulating material; and
removing portions of the encapsulant and portions of the contact posts of the first semiconductor die until the contact posts of the second semiconductor die are exposed.