# US 2021/0242097 A1 · Method of Packaging an Integrated Circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242097 A1 - Document ID: US20210242097A1 - Status: Published application - Kind: A1 - Application number: 17/264,057 - Filed: 2019-07-31 - Published: 2021-08-05 - Earliest claimed: 2018-08-02 - Assignees: Carbon, Inc. - Applicants: Carbon, Inc. - Inventors: William C. HOLTON; James Patrick TROISE; Gurjeev CHADHA; Joseph M. DESIMONE - Web page: https://patentgrep.com/patent/US20210242097A1 ## CPC - H10W 76/15: Containers comprising an insulating or insulated base - B33Y 80/00: Products made by additive manufacturing - H10W 40/251: {Organics} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 72/071: {Connecting or disconnecting} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 76/18: Insulating materials, e.g. resins, glasses or ceramics - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - B29C 64/124: using layers of liquid which are selectively solidified - B29L 2031/3406: {Components, e.g. resistors} - B33Y 10/00: Processes of additive manufacturing - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/682: {comprising holes having chips therein} - H10W 72/01208: {using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks} - H10W 72/073: {of die-attach connectors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/874: {On different surfaces} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B33Y: ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING - B29C: SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING (making preforms B29B11/00; making laminated products by combining previously unconnected layers which become one product whose layers will remain together B32B37/00 - B32B41/00) - B29L: INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES ## Abstract A method of packaging an integrated circuit includes (a) providing: (i) an integrated circuit (e.g., in wafer form) having a two-dimensional contact array on a top surface thereof, (ii) a polymer shell lower portion, and (iii) a polymer shell upper portion, said upper portion having a two-dimensional array of openings formed therein, which array of openings corresponds to said two dimensional contact array; wherein one or both of said polymer shell upper and lower portions are produced by the process of additive manufacturing; and (b) enclosing said integrated circuit between said polymer shell lower portion and said polymer shell upper portion with said contact array aligned with array of openings to produce a integrated circuit packaged within a polymer shell. ## Claims ### Claim 1 A method of packaging an integrated circuit, comprising the steps of: (a) providing: (i) an integrated circuit having a two-dimensional contact array on a top surface thereof, (ii) a polymer shell lower portion, and (iii) a polymer shell upper portion, said upper portion having a two-dimensional array of openings formed therein, which array of openings corresponds to said two dimensional contact array; wherein one or both of said polymer shell upper and lower portions are produced by the process of additive manufacturing; and (b) enclosing said integrated circuit between said polymer shell lower portion and said polymer shell upper portion with said contact array aligned with array of openings to produce a integrated circuit packaged within a polymer shell. ### Claim 2 (depends on 1) The method of claim 1, further comprising: (c) filling said openings with a conductor to produce an external contact array on the surface of said polymer shell corresponding to and in electrical contact with said two-dimensional contact array. ### Claim 3 (depends on 1) The method of claim 1, wherein said integrated circuit is provided without a lead frame, and is enclosed in said polymer shell without a lead frame. ### Claim 4 (depends on 1) The method of claim 1, wherein one or both of said polymer shell upper and lower portions includes at least one heat dissipation feature. ### Claim 5 (depends on 1) The method of claim 1, wherein said polymer shell upper and lower portions both include cooperating interlocking alignment features thereon. ### Claim 6 (depends on 1) The method of claim 1, wherein said process of additive manufacturing comprises a bottom-up or top-down stereolithography process (e.g., continuous liquid interface production, or “CLIP”). ### Claim 7 (depends on 1) The method of claim 1, wherein one or both of said polymer shell upper and lower portions are produced from a dual cure resin. ### Claim 8 (depends on 1) The method of claim 1, wherein said packaged integrated circuit is baked to further cure said polymer shell. ### Claim 9 (depends on 1) The method of claim 1, wherein said encapsulated object comprises multiple interconnected devices. ### Claim 10 A product produced by a process comprising: (a) providing: (i) an integrated circuit having a two-dimensional contact array on a top surface thereof, (ii) a polymer shell lower portion, and (iii) a polymer shell upper portion, said upper portion having a two-dimensional array of openings formed therein, which array of openings corresponds to said two dimensional contact array, wherein one or both of said polymer shell upper and lower portions are produced by the process of additive manufacturing, and (b) enclosing said integrated circuit between said polymer shell lower portion and said polymer shell upper portion with said contact array aligned with array of openings to produce a integrated circuit packaged within a polymer shell. ### Claim 11 A packaged integrated circuit product, comprising: (a) an integrated circuit having a two-dimensional contact array on a top surface thereof, (b) a polymer shell lower portion, and (c) a polymer shell upper portion connected to said polymer shell lower portion with said integrated circuit enclosed therein, said upper portion having a two-dimensional array of openings formed therein, which array of openings corresponds to said two-dimensional contact array; wherein one or both of said polymer shell upper and lower portions are produced by the process of additive manufacturing; and (d) optionally but preferably a conductor filing said openings and providing an external contact array on the surface of said polymer shell corresponding to and electrically connected to said two-dimensional contact array. ### Claim 12 (depends on 11) The product of claim 11, wherein said integrated circuit is enclosed in said polymer shell without a lead frame. ### Claim 13 (depends on 11) The product of claim 11, wherein one or both of said polymer shell upper and lower portions includes at least one heat dissipation feature. ### Claim 14 (depends on 11) The product of claim 11, wherein said polymer shell upper and lower portions both include cooperating interlocking alignment features thereon. ### Claim 15 (depends on 11) The method of claim 11, wherein said process of additive manufacturing comprises a bottom-up or top-down stereolithography process. ### Claim 16 (depends on 11) The product of claim 11, wherein one or both of said polymer shell upper and lower portions are produced from a dual cure resin. ### Claim 17 (depends on 11) The product of claim 11, wherein said encapsulated integrated circuit comprises multiple interconnected devices. ### Claim 18 (depends on 7) The method of claim 7, wherein said dual cure resin comprises an epoxy dual cure resin in a green state that is photopolymerized, but not further cured. ### Claim 19 (depends on 9) The method of claim 9, wherein said multiple interconnected devices comprise two integrated circuits directly connected to one another, said two integrated circuits comprising wafer-level dies packaged together; multiple stacks of dies packaged together; wafer-level dies packaged with other MEMS or optoelectronics; finished dies with MEMS or optoelectronics packaged together; GPU/CPU chips with memory die packaged together (optionally combined with cooling channels etc. in the polymer shell); or multiple NAND die with controller packaged together (optionally combined with cooling channels etc. in the polymer shell)). ### Claim 20 (depends on 11) The product of claim 11, wherein said multiple interconnected devices comprise two integrated circuits directly connected to one another, said two integrated circuits comprising wafer-level dies packaged together; multiple stacks of dies packaged together; wafer-level dies packaged with other MEMS or optoelectronics; finished dies with MEMS or optoelectronics packaged together; GPU/CPU chips with memory die packaged together (optionally combined with cooling channels etc. in the polymer shell); or multiple NAND die with controller packaged together (optionally combined with cooling channels etc. in the polymer shell)).