# US 2021/0242092 A1 · Novel Structures for Tuning Threshold Voltage

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- Number: US 2021/0242092 A1
- Document ID: US20210242092A1
- Status: Published application
- Kind: A1
- Application number: 16/925,893
- Filed: 2020-07-10
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yen-Yu Chen; Chung-Liang Cheng
- Web page: https://patentgrep.com/patent/US20210242092A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

## Claims

### Claim 1

A device, comprising:
a substrate;
an interfacial layer formed over the substrate, wherein the interfacial layer has a dipole-penetrated portion;
a gate dielectric layer formed over the interfacial layer; and
a metal gate electrode formed over the gate dielectric layer.

### Claim 2 (depends on 1)

The device of claim 1, wherein a greatest concentration of a dipole material within the dipole-penetrated portion decreases as a distance from an upper surface of the dipole-penetrated portion increases.

### Claim 3 (depends on 1)

The device of claim 1, wherein a bottom portion of the gate dielectric layer contains a dipole material that is diffused from the interfacial layer.

### Claim 4 (depends on 1)

The device of claim 1, wherein:
the metal gate electrode includes a work function metal component and a fill metal component that is formed over the work function metal component; and
the work function metal component includes a work function metal layer sandwiched between a first protective layer and a second protective layer.

### Claim 5 (depends on 4)

The device of claim 4, wherein the work function metal layer includes TiAlC, and wherein the first protective layer and the second protective layer each include TiN.

### Claim 6 (depends on 1)

The device of claim 1, wherein the device includes a FinFET device or a gate-all-around device.

### Claim 7

A device, comprising:
a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer; and
a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer;
wherein the first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

### Claim 8 (depends on 7)

The device of claim 7, wherein:
a peak concentration of the dipole material in the first interfacial layer occurs at an interface between the first interfacial layer and the first gate dielectric layer; or
a peak concentration of the dipole material in the second interfacial layer occurs at an interface between the second interfacial layer and the second gate dielectric layer.

### Claim 9 (depends on 7)

The device of claim 7, wherein:
a first portion of the first interfacial layer contains the dipole material, the first portion having a first depth or a first dipole concentration level; and
a second portion of the second interfacial layer contains the dipole material, the second portion having a second depth that is different from the first depth or a second dipole concentration level that is different from the first dipole concentration level.

### Claim 10 (depends on 7)

The device of claim 7, wherein:
the first gate structure is associated with a first threshold voltage; and
the second gate structure is associated with a second threshold voltage that is different from the first threshold voltage.

### Claim 11 (depends on 7)

The device of claim 7, wherein the dipole material is a first dipole material, and wherein the device further comprises:
a third gate structure that includes a third interfacial layer, a third gate dielectric layer disposed over the third interfacial layer, and a third gate electrode disposed over the third gate dielectric layer; and
a fourth gate structure that includes a fourth interfacial layer, a fourth gate dielectric layer disposed over the fourth interfacial layer, and a fourth gate electrode disposed over the fourth gate dielectric layer;
wherein:
the third interfacial layer contains a different amount of a second dipole material than the fourth interfacial layer;
the first gate structure and the second gate structure are components of N-type transistors; and
the third gate structure and the fourth gate structure are components of P-type transistors.

### Claim 12 (depends on 11)

The device of claim 11, wherein the first dipole material and the second dipole material are both N-type dipole materials or are both P-type dipole materials.

### Claim 13 (depends on 11)

The device of claim 11, wherein:
the first dipole material includes an N-type dipole material; and
the second dipole material includes a P-type dipole material.

### Claim 14

A method, comprising:
forming a mask layer over a first interfacial layer (IL) for a first gate structure and over a second IL for a second gate structure;
patterning the mask layer to remove a portion of the mask layer formed over the first IL;
forming a dipole layer, wherein a first portion of the dipole layer is formed directly on the first IL, and wherein a second portion of the dipole layer is formed on a remaining portion of the mask layer disposed over the second IL; and
performing a dipole drive-in process to drive in a material of the dipole layer into the first IL and the second IL.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the dipole drive-in process forms a first dipole-penetrated portion in the first IL and a second dipole-penetrated portion in the second IL;
the first dipole-penetrated portion has a first depth;
the second dipole-penetrated portion has a second depth; and
the first depth is greater than the second depth.

### Claim 16 (depends on 14)

The method of claim 14, wherein after the dipole drive-in process has been performed:
the first IL has a first concentration level of the material of the dipole layer;
the second IL has a second concentration level of the material of the dipole layer; and
the first concentration level is greater than the second concentration level.

### Claim 17 (depends on 14)

The method of claim 14, wherein the dipole drive-in process comprises an annealing process performed in a temperature range between about 600 degrees Celsius and 800 degrees Celsius and with a nitrogen gas.

### Claim 18 (depends on 14)

The method of claim 14, further comprising:
removing the dipole layer and removing the remaining portion of the mask layer after the dipole drive-in process has been performed;
forming a gate dielectric layer directly on the first IL and the second IL;
forming one or more work function metal layers over the gate dielectric layer; and
forming a fill metal over the one or more work function metal layers.

### Claim 19 (depends on 18)

The method of claim 18, wherein the forming the one or more work function metal layers comprises:
forming a first work function metal layer over the gate dielectric layer;
forming a second work function metal layer over the first work function metal layer; and
forming a third work function metal layer over the second work function metal layer;
wherein:
the first work function metal layer and the third work function metal layer have same material compositions; and
the second work function metal layer has a different material composition than the first work function metal layer and the third work function metal layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first work function metal layer, the second work function metal layer, and the third work function metal layer are formed in-situ using a same deposition tool.