# US 2021/0242090 A1 · Etch Stop Layer Between Substrate and Isolation Structure

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- Number: US 2021/0242090 A1
- Document ID: US20210242090A1
- Status: Published application
- Kind: A1
- Application number: 17/240,007
- Filed: 2021-04-26
- Published: 2021-08-05
- Earliest claimed: 2017-11-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ming-Chang Wen; Chang-Yun Chang; Hsien-Chin Lin; Hung-Kai Chen
- Web page: https://patentgrep.com/patent/US20210242090A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a substrate; semiconductor fins extending from the substrate; a liner layer on sidewalls of the semiconductor fins; an etch stop layer over the substrate and extending laterally from a first portion of the liner layer on a first one of the semiconductor fins to a second portion of the line layer on a second one of the semiconductor fins; an isolation structure over the etch stop layer, wherein the etch stop layer and the isolation structure include different materials; a gate dielectric layer over a top surface of the isolation structure; and a dielectric feature extending through the gate dielectric layer and into the isolation structure, wherein the isolation structure and the dielectric feature collectively extend laterally from the first portion of the liner layer to the second portion of the line layer.

## Claims

### Claim 1

A device, comprising:
a substrate;
semiconductor fins extending from the substrate;
a liner layer on sidewalls of the semiconductor fins;
an etch stop layer over the substrate and extending laterally from a first portion of the liner layer on a first one of the semiconductor fins to a second portion of the line layer on a second one of the semiconductor fins;
an isolation structure over the etch stop layer, wherein the etch stop layer and the isolation structure include different materials;
a gate dielectric layer over a top surface of the isolation structure; and
a dielectric feature extending through the gate dielectric layer and into the isolation structure, wherein the isolation structure and the dielectric feature collectively extend laterally from the first portion of the liner layer to the second portion of the line layer.

### Claim 2 (depends on 1)

The device of claim 1, wherein the dielectric feature is physically separated from the etch stop layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein the dielectric feature physically contacts the etch stop layer.

### Claim 4 (depends on 1)

The device of claim 1, wherein the etch stop layer includes alumina (Al2O3), tungsten carbide (WC), or yttrium silicon oxide (YSiOx).

### Claim 5 (depends on 1)

The device of claim 1, wherein the etch stop layer includes include silicon and one of: carbon, germanium, arsenic, and phosphorus.

### Claim 6 (depends on 1)

The device of claim 1, wherein the etch stop layer includes an III-V compound.

### Claim 7 (depends on 6)

The device of claim 6, wherein the III-V compound includes one of gallium arsenide, gallium phosphide, gallium nitride, and indium arsenide.

### Claim 8 (depends on 1)

The device of claim 1, wherein the semiconductor fins include silicon, the liner layer includes silicon nitride, the etch stop layer includes silicon germanium, and the isolation structure includes silicon oxide.

### Claim 9 (depends on 1)

The device of claim 1, further comprising a gate electrode layer over the gate dielectric layer, wherein the dielectric feature also extends through the gate electrode layer.

### Claim 10

A device, comprising:
a substrate;
semiconductor fins over the substrate;
an etch stop layer over the substrate and laterally between lower portions of two adjacent semiconductor fins;
an isolation structure over the etch stop layer and laterally between the lower portions of the two adjacent semiconductor fins, wherein the semiconductor fins extend above a top surface of the isolation structure;
a gate dielectric layer over the isolation structure and the semiconductor fins;
a conductive layer over the gate dielectric layer; and
a dielectric feature penetrating through the conductive layer, the gate dielectric layer, and the isolation structure and reaching the etch stop layer, wherein the etch stop layer and the isolation structure include different materials.

### Claim 11 (depends on 10)

The device of claim 10, wherein the semiconductor fins include silicon, the etch stop layer includes silicon germanium, the isolation structure includes silicon oxide, and the dielectric feature includes silicon nitride.

### Claim 12 (depends on 10)

The device of claim 10, further comprising a dielectric liner layer on sidewalls of the lower portions of the two adjacent semiconductor fins and laterally between the semiconductor fins and the isolation structure.

### Claim 13 (depends on 12)

The device of claim 12, wherein the etch stop layer and the dielectric liner layer include different materials.

### Claim 14 (depends on 10)

The device of claim 10, wherein the etch stop layer includes silicon germanium, silicon arsenide, or silicon phosphide.

### Claim 15 (depends on 10)

The device of claim 10, wherein the etch stop layer includes alumina, tungsten carbide, yttrium silicon oxide, or an III-V compound.

### Claim 16 (depends on 10)

The device of claim 10, wherein the etch stop layer physically contacts the substrate.

### Claim 17

A device, comprising:
a substrate including silicon;
semiconductor fins over the substrate;
a dielectric liner layer on sidewalls of the semiconductor fins;
an etch stop layer over the substrate and laterally between a first one and a second one of the semiconductor fins;
an isolation structure over the etch stop layer, wherein the semiconductor fins extend above a top surface of the isolation structure;
a high-k metal gate structure over the isolation structure, the dielectric liner layer, and the semiconductor fins; and
a dielectric feature penetrating through the high-k metal gate structure and reaching into the isolation structure, wherein the etch stop layer includes a material different than that of the isolation structure, wherein a combination of the isolation structure and the dielectric feature extend laterally from a first portion of the dielectric liner layer on the first one of the semiconductor fins to a second portion of the dielectric line layer on the second one of the semiconductor fins.

### Claim 18 (depends on 17)

The device of claim 17, wherein the etch stop layer physically contacts the substrate and includes silicon germanium, silicon arsenide, or silicon phosphide.

### Claim 19 (depends on 17)

The device of claim 17, wherein the etch stop layer includes alumina, tungsten carbide, yttrium silicon oxide, or an III-V compound.

### Claim 20 (depends on 17)

The device of claim 17, wherein the dielectric feature physically contacts the etch stop layer.