# US 2021/0242087 A1 · Method for fabricating a device comprising a pnp bipolar transistor and npn bipolar transistor for radiofrequency applications

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- Number: US 2021/0242087 A1
- Document ID: US20210242087A1
- Status: Published application
- Kind: A1
- Application number: 17/160,598
- Filed: 2021-01-28
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: STMicroelectronics (Crolles 2) SAS
- Applicants: STMicroelectronics (Crolles 2) SAS
- Inventors: Jean JIMENEZ MARTINEZ
- Web page: https://patentgrep.com/patent/US20210242087A1

## CPC

- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10D 84/673: {Vertical complementary BJTs}
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 62/137: {Collector regions of BJTs}
- H10D 84/0121: {the complementary BJTs being vertical BJTs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

## Claims

### Claim 1

A method for fabricating a microelectronic device that includes a PNP transistor and an NPN transistor, comprising:
forming an N+ doped isolating well of the PNP transistor in a P-type doped semiconductor substrate;
forming a P+ doped region in the N+ doped isolating well;
epitaxially growing a first epitaxial semiconductor layer on the semiconductor substrate;
forming an N+ doped well of the NPN transistor, wherein at least part of said N+ doped well extends into the first epitaxial semiconductor layer;
after forming the N+ doped well, epitaxially growing a second epitaxial semiconductor layer on the first epitaxial semiconductor layer;
forming a P doped region configured to form a collector of the PNP transistor in the second epitaxial semiconductor layer, wherein said P doped region is in electrical contact with the P+ doped region in the N+ doped well; and
forming an N doped region configured to form a collector of the NPN transistor in the second epitaxial semiconductor layer, wherein the N doped region is in electrical contact with the N+ doped well.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first epitaxial semiconductor layer has a thickness of between 0.5 and 0.7 μm.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the first epitaxial semiconductor layer is lightly P doped.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the first epitaxial semiconductor layer is non-intentionally doped.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the second epitaxial semiconductor layer has a thickness of between 0.3 and 0.5 μm.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the second epitaxial semiconductor layer is lightly N-doped.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the second epitaxial semiconductor layer is non-intentionally doped.

### Claim 8 (depends on 1)

The method according to claim 1, wherein a sum of thicknesses of the first and second epitaxial semiconductor layers is between 0.8 and 1.2 μm.

### Claim 9

A microelectronic device including a PNP transistor and NPN transistor, comprising:
a semiconductor substrate;
a P+ doped region in the semiconductor substrate;
wherein a collector of the PNP transistor is arranged on the P+ doped region in the semiconductor substrate;
an N+ doped well in the semiconductor substrate;
wherein a collector of the NPN transistor is arranged on the N+ doped well in the semiconductor substrate;
wherein said P+ doped region for the PNP transistor extends at least partly into a first epitaxial semiconductor layer; and
wherein the N+ doped well for the NPN transistor extends at least partly into a second epitaxial semiconductor layer arranged on the first epitaxial semiconductor layer;
wherein the P+ doped region for the PNP transistor is located farther from an upper device surface of the microelectronic device than the N+ doped well for the NPN transistor.

### Claim 10 (depends on 9)

The device according to claim 9, wherein the first epitaxial semiconductor layer has a thickness of between 0.5 and 0.7 μm.

### Claim 11 (depends on 9)

The device according to claim 9, wherein the first epitaxial semiconductor layer is lightly P-doped.

### Claim 12 (depends on 9)

The device according to claim 9, wherein the first epitaxial semiconductor layer is non-intentionally doped.

### Claim 13 (depends on 9)

The device according to claim 9, wherein the second epitaxial semiconductor layer has a thickness of between 0.3 and 0.5 μm.

### Claim 14 (depends on 9)

The device according to claim 9, wherein the second epitaxial semiconductor layer is lightly N-doped.

### Claim 15 (depends on 9)

The device according to claim 9, wherein the second epitaxial semiconductor layer is non-intentionally doped.

### Claim 16 (depends on 9)

The device according to claim 9, wherein a sum of the thicknesses of the first and second epitaxial semiconductor layers is between 0.8 and 1.2 μm.