# US 2021/0242083 A1 · Processes for Reducing Leakage and Improving Adhesion

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0242083 A1
- Document ID: US20210242083A1
- Status: Published application
- Kind: A1
- Application number: 17/215,246
- Filed: 2021-03-29
- Published: 2021-08-05
- Earliest claimed: 2018-04-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yun Chen Hsieh; Hui-Jung Tsai; Hung-Jui Kuo; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US20210242083A1

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10W 20/048: {by using plasmas or gaseous environments, e.g. by nitriding}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/90: Bond pads, in general
- H10W 74/016: {using moulds}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/655: Fan-out layouts
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/01257: {by reflowing}
- H10W 72/01336: {in solid form, e.g. by using a powder or by laminating a foil}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/473: {containing a filler}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.

## Claims

### Claim 1

A method comprising:
forming a metal seed layer on a dielectric layer;
forming a patterned plating mask over the metal seed layer, wherein an opening in the patterned plating mask is over a first portion of the dielectric layer, and the patterned plating mask overlaps a second portion of the dielectric layer;
plating a metal post in the opening;
removing the patterned plating mask to expose portions of the metal seed layer;
etching the exposed portions of the metal seed layer to reveal the second portion of the dielectric layer;
oxidizing the metal post; and
encapsulating the metal post in an encapsulant.

### Claim 2 (depends on 1)

The method of claim 1, wherein the oxidizing is performed using process gases comprising oxygen (O2) and an additional gas, wherein the additional gas is selected from the group consisting of Ar, nitrogen (N2), a combination thereof.

### Claim 3 (depends on 2)

The method of claim 2, wherein the oxidizing is performed with plasma being generated from the process gases.

### Claim 4 (depends on 2)

The method of claim 2, wherein the oxidizing is performed with a bias power applied.

### Claim 5 (depends on 1)

The method of claim 1 further comprising, after the oxidizing, etching metal-containing particles left on the dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the oxidizing generates a metal oxide layer on surfaces of the metal post, and the encapsulating the metal post is performed after the oxidizing.

### Claim 7 (depends on 6)

The method of claim 6, wherein the metal oxide layer physically separates the metal post from the encapsulant.

### Claim 8 (depends on 1)

The method of claim 1 further comprising:
forming an Under-Bump Metallurgy (UBM) overlying and electrically coupling to the metal post;
oxidizing the UBM; and
performing an etching process on the oxidized UBM.

### Claim 9 (depends on 1)

The method of claim 1, wherein the metal seed layer comprises a first layer and a second layer over the first layer, and the oxidizing is performed after the second layer is etched.

### Claim 10

A method comprising:
forming a metal post over a carrier;
performing a first oxidation process using an oxygen-containing gas to oxidize a surface layer of the metal post, wherein a metal oxide layer is formed at surfaces of the metal post;
placing a device die over the carrier;
encapsulating the metal post and the device die in an encapsulant, wherein the metal oxide layer is in contact with the encapsulant;
performing a planarization process on the encapsulant, the metal post, and the device die; and
forming a redistribution structure over and electrically connecting to the metal post and the device die.

### Claim 11 (depends on 10)

The method of claim 10, wherein the planarization process is performed until a portion of the metal oxide layer on top of the metal post is removed to reveal the metal post.

### Claim 12 (depends on 10)

The method of claim 10, wherein the first oxidation process is performed using plasma.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first oxidation process is performed with a bias power applied.

### Claim 14 (depends on 10)

The method of claim 10 further comprising, before the first oxidation process:
performing a second oxidation process to form an additional metal oxide layer on the metal post; and
removing the additional metal oxide layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second oxidation process is performed with plasma.

### Claim 16 (depends on 14)

The method of claim 14, wherein the first oxidation process is performed with a first bias power applied, and the second oxidation process is performed with a second bias power applied, and wherein the first bias power is lower than the second bias power.

### Claim 17

A method comprising:
forming a metal post over a carrier;
removing a first metal oxide layer on the metal post to reveal a metal of the metal post;
after the first metal oxide layer is removed, oxidizing the metal post to form a second metal oxide layer on surfaces of the metal post;
encapsulating the metal post and a device die in an encapsulant;
planarizing the encapsulant, the metal post, and the device die until the metal post is removed, wherein a portion of the second metal oxide layer is left between the metal post and the encapsulant; and
forming a redistribution structure over and electrically connecting to the metal post.

### Claim 18 (depends on 17)

The method of claim 17 further comprising, before the removing the first metal oxide layer, performing a plasma oxidation process to generate the first metal oxide layer on the surfaces of the metal post.

### Claim 19 (depends on 18)

The method of claim 18, wherein the plasma oxidation process is performed with a first bias power applied, and the second metal oxide layer is formed with a second bias power applied, and the first bias power is higher than the second bias power.

### Claim 20 (depends on 17)

The method of claim 17, wherein the portion of the second metal oxide layer physically contacts both of the metal post and the encapsulant.