# US 2021/0242081 A1 · Selective Hybrid Capping Layer for Metal Gates of Transistors

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- Number: US 2021/0242081 A1
- Document ID: US20210242081A1
- Status: Published application
- Kind: A1
- Application number: 16/884,837
- Filed: 2020-05-27
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chung-Chiang Wu; Po-Cheng Chen; Kuo-Chan Huang; Pin-Hsuan Yeh; Wei-Chin Lee; Hsien-Ming Lee; Chien-Hao Chen; Chi On Chui
- Web page: https://patentgrep.com/patent/US20210242081A1

## CPC

- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10W 20/033: {in openings in dielectrics}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

## Claims

### Claim 1

A method comprising:
forming a gate electrode over a semiconductor region;
recessing the gate electrode to generate a recess;
performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor;
performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor, wherein the first metallic layer and the second metallic layer comprise a same metal;
forming a dielectric hard mask over the second metallic layer; and
forming a gate contact plug penetrating through the dielectric hard mask, wherein the gate contact plug contacts a top surface of the second metallic layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first precursor comprises tungsten chloride (WCl5), and the second precursor comprises tungsten fluoride (WF6).

### Claim 3 (depends on 1)

The method of claim 1, wherein in the first deposition process, surfaces of dielectric materials adjacent to the gate electrode are exposed, and the first deposition process is stopped before the first metal layer starts growing on exposed dielectric materials adjacent to the gate electrode.

### Claim 4 (depends on 1)

The method of claim 1, wherein each of the first deposition process and the second deposition process comprises an atomic layer deposition process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the recessing the gate electrode comprises:
a first recessing process to recess the gate electrode, a gate dielectric, and gate spacers, wherein the gate dielectric comprises first sidewall portions on sidewalls of the gate electrode, and the gate electrode and the gate spacers are between the gate spacers; and
a second recessing process to recess the gate electrode to be lower than top edges of the gate dielectric.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first metallic layer has a first thickness smaller than about 3 nm.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second metallic layer has a second thickness greater than about 3 nm.

### Claim 8

A device comprising:
a semiconductor region;
a gate dielectric over the semiconductor region;
a gate electrode comprising:
a first portion comprising a work-function layer therein; and
a second portion overlying and contacting the first portion, wherein the second portion comprises fluorine and chlorine, and wherein the second portion comprises:
a bottom sub layer, wherein a first peak atomic percentage of fluorine is in the bottom sub layer; and
a top sub layer over and contacting the bottom sub layer, wherein a second peak atomic percentage of fluorine is in the top sub layer, and wherein the bottom sub layer and the top sub layer comprise a same metal; and
a gate contact plug over and contacting the top sub layer.

### Claim 9 (depends on 8)

The device of claim 8, wherein the first portion comprises titanium, and the second portion comprises tungsten.

### Claim 10 (depends on 8)

The device of claim 8, wherein the bottom sub layer and the top sub layer are distinguishable through Transmission electron microscopy (TEM).

### Claim 11 (depends on 8)

The device of claim 8, wherein the gate dielectric comprises sidewall portions, and a bottom portion underlying and connected to the sidewall portions, and wherein the first portion and the second portion of the gate electrode are between the sidewall portions.

### Claim 12 (depends on 11)

The device of claim 11, wherein a top surface of the top sub layer is level with or lower than top edges of the sidewall portions of the gate dielectric.

### Claim 13 (depends on 8)

The device of claim 8 further comprising:
gate spacers on opposing sides of the gate dielectric and the gate electrode; and
an inter-layer dielectric, with the gate spacers in the inter-layer dielectric, wherein a first top surface of the gate dielectric is recessed lower than a second top surface of the inter-layer dielectric.

### Claim 14 (depends on 13)

The device of claim 13, wherein the gate spacers are recessed to have a third top surface lower than the second top surface.

### Claim 15

A device comprising:
a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a semiconductor fin protruding higher than portions of the isolation regions on opposing sides of the semiconductor fin; and
a gate stack comprising:
a high-k gate dielectric on the semiconductor fin;
a work function layer on the high-k gate dielectric;
a capping layer;
a first tungsten layer over and contacting the work function layer and the capping layer; and
a second tungsten layer over and contacting the first tungsten layer, wherein the first tungsten layer and the second tungsten layer are distinguishable from each other.

### Claim 16 (depends on 15)

The device of claim 15, wherein both of the first tungsten layer and the second tungsten layer comprise fluorine and chlorine, and wherein a first peak atomic percentage of fluorine is in the first tungsten layer.

### Claim 17 (depends on 16)

The device of claim 16, wherein a second peak atomic percentage of fluorine is in the second tungsten layer.

### Claim 18 (depends on 15)

The device of claim 15, wherein both of the first tungsten layer and the second tungsten layer comprise nitrogen, and wherein nitrogen atomic percentages in the gate stack has a peak at an interface between the first tungsten layer and the second tungsten layer.

### Claim 19 (depends on 15)

The device of claim 15, wherein the high-k gate dielectric comprises sidewall portions on opposing sides of the first tungsten layer and the second tungsten layer, and a top surface of the second tungsten layer is between, and is level with or lower than top edges of the sidewall portions of the high-k gate dielectric.

### Claim 20 (depends on 0)

The device of claim 0, wherein the capping layer comprises titanium nitride.