# US 2021/0242080 A1 · Protection Structures for Bonded Wafers

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- Number: US 2021/0242080 A1
- Document ID: US20210242080A1
- Status: Published application
- Kind: A1
- Application number: 17/238,496
- Filed: 2021-04-23
- Published: 2021-08-05
- Earliest claimed: 2018-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ssu-Chiang Weng; Ping-Hao Lin; Fu-Cheng Chang
- Web page: https://patentgrep.com/patent/US20210242080A1

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10P 50/283: {by chemical means}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/213: {Cross-sectional shapes or dispositions}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 90/00: Package configurations
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

## Claims

### Claim 1

A structure comprising:
a first die comprising:
a first semiconductor substrate;
a plurality of dielectric layers underlying the first semiconductor substrate;
a plurality of metal rings, each in one of the plurality of dielectric layers, wherein inner lateral dimensions of the plurality of metal rings are different from each other, and wherein the plurality of metal rings are stacked to form a metal pipe; and
a first surface dielectric layer underlying the plurality of metal rings and the plurality of dielectric layers;
a second die comprising:
a second semiconductor substrate;
a metal pad over the second semiconductor substrate;
a second surface dielectric layer overlying the metal pad, wherein the first surface dielectric layer is bonded to the second surface dielectric layer; and
a conductive plug penetrating through the first die to contact a top surface of the metal pad.

### Claim 2 (depends on 1)

The structure of claim 1 further comprising a dielectric protection layer comprising a first portion encircling the conductive plug, wherein the first portion of the dielectric protection layer contacts sidewalls of the first surface dielectric layer and the second surface dielectric layer.

### Claim 3 (depends on 2)

The structure of claim 2, wherein the dielectric protection layer further comprises a second portion encircling the conductive plug, wherein the second portion of the dielectric protection layer is physically separated from the first portion, and extends into the first semiconductor substrate.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the conductive plug has a portion in the metal pipe, and from a top to a bottom of the portion of the conductive plug, the, lateral diameters of the portion of the conductive plug gradually decrease.

### Claim 5 (depends on 1)

The structure of claim 1, wherein the plurality of metal rings comprise a plurality of damascene structures, with each having a metal-line portion and a via portion overlying the metal-line portion, and the via portion has a first inner lateral dimension smaller than a second inner lateral dimension of the metal-line portion.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the second die further comprises an etch stop layer over and contacting the metal pad, with the conductive plug penetrating through the etch stop layer.

### Claim 7 (depends on 1)

The structure of claim 1, wherein the first die further comprises an additional dielectric layer comprising a vertical portion extending into the first semiconductor substrate, and a first horizontal portion overlapping the first semiconductor substrate.

### Claim 8 (depends on 7)

The structure of claim 7, wherein the additional dielectric layer further comprises a second horizontal portion at a bottom of the first semiconductor substrate, wherein the second horizontal portion is underlying and connected to the vertical portion.

### Claim 9

A structure comprising:
a first die comprising:
a first semiconductor substrate;
a plurality of dielectric layers underlying the first semiconductor substrate;
a metal ring extending into the plurality of dielectric layers; and
a dielectric layer, wherein a vertical portion of the dielectric layer is on a sidewall of the first semiconductor substrate;
a second die bonded to the first die, the second die comprising:
a second semiconductor substrate; and
a metal pad over the second semiconductor substrate; and
a conductive plug extending into the first die and the second die, and contacting a top surface of the metal pad, wherein the conductive plug comprises:
a first portion encircled by the metal ring, wherein lower parts of the first portion are increasingly narrower than respective upper portions of the first portion; and
a second portion in the first semiconductor substrate, wherein the second portion is spaced apart from the first semiconductor substrate by the first portion of the dielectric layer.

### Claim 10 (depends on 9)

The structure of claim 9, wherein the metal ring further comprises a plurality of sub-rings, each in one of the plurality of dielectric layers, wherein each of the plurality of sub-rings comprises a line portion and a via portion over the line portion, and the via portion encircles a wider portion of the conductive plug than the respective line portion.

### Claim 11 (depends on 10)

The structure of claim 10, wherein outer edges of the line portions of the plurality of sub-rings are vertically aligned.

### Claim 12 (depends on 10)

The structure of claim 10, wherein the plurality of sub-rings are stacked to form the metal ring that extends continuously from an additional top surface of the first semiconductor substrate to the second die.

### Claim 13 (depends on 9)

The structure of claim 9, wherein the dielectric layer further comprises a horizontal portion overlapping the first semiconductor substrate.

### Claim 14 (depends on 9)

The structure of claim 9 further comprising a first protection layer in the first semiconductor substrate, wherein the first protection layer is encircled by the vertical portion of the dielectric layer.

### Claim 15 (depends on 14)

The structure of claim 14, wherein the first protection layer forms a ring encircling a top part of the conductive plug.

### Claim 16 (depends on 14)

The structure of claim 14 further comprising a second protection layer encircling a bottom portion of the conductive plug, wherein the first protection layer and the second protection layer are formed of a same dielectric material, and a spaced apart from each other.

### Claim 17 (depends on 9)

The structure of claim 9 further comprising an additional dielectric layer over and contacting the conductive plug, wherein the additional dielectric layer further extends directly over the first semiconductor substrate.

### Claim 18

A structure comprising:
a first die comprising:
a first semiconductor substrate;
a plurality of dielectric layers underlying the first semiconductor substrate; and
a plurality of metal rings, each in one of the plurality of dielectric layers;
a second die bonding to the first die, the second die comprising:
a second semiconductor substrate;
a metal pad over the second semiconductor substrate; and
a conductive plug penetrating through the first die to contact a top surface of the metal pad, wherein the conductive plug comprises a portion in the first die, and the portion has increasingly smaller lateral dimensions, and wherein sidewalls of the portion of the conductive plug comprises steps.

### Claim 19 (depends on 18)

The structure of claim 18, wherein each of the plurality of metal rings further comprises an upper portion and a lower portion, wherein the upper portion has a first internal dimension greater than a second internal dimension of the lower portion.

### Claim 20 (depends on 18)

The structure of claim 18 further comprising:
a first protection layer in the first semiconductor substrate and encircling a top portion of the conductive plug; and
a second protection layer encircling a bottom portion of the conductive plug, wherein the first protection layer and the second protection layer are formed of a same dielectric material, and are separate from each other by the plurality of metal rings.