# US 2021/0242079 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0242079 A1 - Document ID: US20210242079A1 - Status: Published application - Kind: A1 - Application number: 17/215,365 - Filed: 2021-03-29 - Published: 2021-08-05 - Earliest claimed: 2018-07-19 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Moon Keun KIM; Jae Wha PARK; Jun Kwan KIM; Hyo Jeong MOON; Seung Jong PARK; Seul Gi BAE - Web page: https://patentgrep.com/patent/US20210242079A1 ## CPC - H10W 20/071: {of dielectric parts thereof} - H10W 20/075: {of multilayered thin functional dielectric layers} - H10P 14/6336: {in the presence of a plasma [PECVD]} - H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane} - H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/0633: {using subtractive patterning of the conductive members} - H10W 20/076: {in via holes or trenches} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 20/42: Vias, e.g. via plugs - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W 20/48: Insulating materials thereof - H10W 20/063: {by forming conductive members before forming protective insulating material} - H10W 20/072: {of dielectric parts comprising air gaps} - H10W 20/46: comprising air gaps - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen. ## Claims ### Claim at position 1 1-20. (canceled) ### Claim 21 A semiconductor device, comprising: a substrate; a first interlayer insulating layer disposed on the substrate; a lower wiring disposed in the first interlayer insulating layer and including copper; a first insulating layer disposed on the first interlayer insulating layer and including at least one of silicon nitride, silicon oxynitride, and silicon carbon nitride; a second interlayer insulating layer disposed on the first insulating layer; a contact structure passing through the second interlayer insulating layer and the first insulating layer, and contacting the lower wiring, the contact structure including tungsten; a third interlayer insulating layer disposed on and contacting the second interlayer insulating layer; a first upper wiring disposed in the third interlayer insulating layer and contacting the contact structure, the first upper wiring including aluminum; and a second insulating layer disposed on and contacting the third interlayer insulating layer, the second insulating layer including at least one of silicon nitride, silicon oxynitride, and silicon carbon nitride, wherein: the third interlayer insulating layer includes deuterium, and a top surface of the first upper wiring is disposed lower than a top surface of the third interlayer insulating layer. ### Claim 22 (depends on 21) The semiconductor device of claim 21, further comprising a second upper wiring that is disposed adjacent to the first upper wiring and in the third interlayer insulating layer, wherein the third interlayer insulating layer includes an air gap that is disposed between the first upper wiring and the second upper wiring. ### Claim 23 (depends on 21) The semiconductor device of claim 21, wherein the top surface and a side surface of the first upper wiring are in contact with the third interlayer insulating layer. ### Claim 24 (depends on 21) The semiconductor device of claim 21, wherein a bottom surface of the first upper wiring is substantially coplanar with a top surface of the second interlayer insulating layer. ### Claim 25 (depends on 21) The semiconductor device of claim 21, wherein a top surface of the lower wiring is substantially coplanar with a top surface of the first interlayer insulating layer. ### Claim 26 (depends on 21) The semiconductor device of claim 21, wherein: the first upper wiring includes a first wiring pattern, a second wiring pattern that is disposed on the first wiring pattern, and a third wiring pattern that is disposed on the second wiring pattern, a bottom surface of the first wiring pattern of the first upper wiring contacts a top surface of the contact structure and a top surface of the second interlayer insulating layer, and a top surface of the third wiring pattern of the first upper wiring contacts the third interlayer insulating layer. ### Claim 27 (depends on 26) The semiconductor device of claim 26, wherein a side surface of each of the first wiring pattern, the second wiring pattern, and the third wiring pattern of the first upper wiring contacts the third interlayer insulating layer. ### Claim 28 (depends on 21) The semiconductor device of claim 21, wherein a bottom surface of the first insulating layer contacts a top surface of the lower wiring. ### Claim 29 (depends on 21) The semiconductor device of claim 21, wherein a top surface of the contact structure is substantially coplanar with a top surface of the second interlayer insulating layer. ### Claim 30 (depends on 21) The semiconductor device of claim 21, further comprising a third upper wiring that passes through a portion of the third interlayer insulating layer and the second insulating layer, and contacts the top surface of the first upper wiring, wherein the third upper wiring extends over the top surface of the third interlayer insulating layer. ### Claim 31 A semiconductor device, comprising: a substrate; a first interlayer insulating layer disposed on the substrate; a lower wiring disposed in the first interlayer insulating layer; a first insulating layer disposed on the first interlayer insulating layer; a second interlayer insulating layer disposed on the first insulating layer; a contact structure passing through the second interlayer insulating layer and the first insulating layer, and contacting the lower wiring; a third interlayer insulating layer disposed on and contacting the second interlayer insulating layer; a first upper wiring disposed in the third interlayer insulating layer and contacting the contact structure; and a second insulating layer disposed on and contacting the third interlayer insulating layer, wherein: the lower wiring is electrically connected to the substrate, a top surface of the lower wiring is substantially coplanar with a top surface of the first interlayer insulating layer and contacts a bottom surface of the first insulating layer, a top surface of the contact structure is substantially coplanar with a top surface of the second interlayer insulating layer, the third interlayer insulating layer includes deuterium, a bottom surface of the first upper wiring contacts the top surface of the contact structure and the top surface of the second interlayer insulating layer; and a top surface and a side surface of the first upper wiring are in contact with the third interlayer insulating layer. ### Claim 32 (depends on 31) The semiconductor device of claim 31, wherein the top surface of the first upper wiring is disposed lower than a top surface of the third interlayer insulating layer. ### Claim 33 (depends on 31) The semiconductor device of claim 31, further comprising a second upper wiring that is disposed adjacent to the first upper wiring and in the third interlayer insulating layer, wherein the third interlayer insulating layer includes an air gap that is disposed between the first upper wiring and the second upper wiring. ### Claim 34 (depends on 31) The semiconductor device of claim 31, further comprising a third upper wiring that passes through a portion of the third interlayer insulating layer and the second insulating layer, and contacts the top surface of the first upper wiring, wherein the third upper wiring extends over a top surface of the third interlayer insulating layer. ### Claim 35 (depends on 31) The semiconductor device of claim 31, wherein each of the first insulating layer and the second insulating layer includes at least one of silicon nitride, silicon oxynitride, and silicon carbon nitride. ### Claim 36 (depends on 31) The semiconductor device of claim 31, wherein the lower wiring includes copper, the first upper wiring includes aluminum, and the contact structure includes tungsten. ### Claim 37 A semiconductor device, comprising: a substrate; a first interlayer insulating layer disposed on the substrate; a lower wiring disposed in the first interlayer insulating layer and electrically connected to the substrate; a first insulating layer disposed on the first interlayer insulating layer and including at least one of silicon nitride, silicon oxynitride, and silicon carbon nitride; a second interlayer insulating layer disposed on the first insulating layer; a contact structure passing through the second interlayer insulating layer and the first insulating layer, and contacting the lower wiring; a second insulating layer disposed on the second interlayer insulating layer and including at least one of silicon nitride, silicon oxynitride, and silicon carbon nitride; a third interlayer insulating layer disposed on the second insulating layer; and an upper wiring disposed in the second insulating layer and the third interlayer insulating layer, and contacting the contact structure, wherein: a top surface of the lower wiring is substantially coplanar with a top surface of the first interlayer insulating layer and contacts a bottom surface of the first insulating layer, a top surface of the contact structure is substantially coplanar with a top surface of the second interlayer insulating layer, the third interlayer insulating layer includes deuterium, the contact structure contacts the first insulating layer and is spaced apart from the second insulating layer, a top surface of the upper wiring is substantially coplanar with a top surface of the third interlayer insulating layer, a side surface of the upper wiring contacts the third interlayer insulating layer and the second insulating layer, and a width of the top surface of the upper wiring is greater than a width of a bottom surface of the upper wiring. ### Claim 38 (depends on 37) The semiconductor device of claim 37, wherein the lower wiring includes copper, the upper wiring includes aluminum, and the contact structure includes tungsten. ### Claim 39 A semiconductor device, comprising: a substrate; a first interlayer insulating layer disposed on the substrate; a lower wiring disposed in the first interlayer insulating layer and electrically connected to the substrate; an insulating layer disposed on the first interlayer insulating layer and including at least one of silicon nitride, silicon oxynitride, and silicon carbon nitride; a second interlayer insulating layer disposed on the insulating layer; and an upper wiring disposed in the insulating layer and the second interlayer insulating layer, and contacting the lower wiring, the upper wiring including a first portion and a second portion that is disposed on the first portion, wherein: a top surface of the lower wiring is substantially coplanar with a top surface of the first interlayer insulating layer and contacts a bottom surface of the insulating layer, the second interlayer insulating layer includes deuterium, a side surface of the first portion of the upper wiring contacts the insulating layer and the second interlayer insulating layer, a top surface of the second portion of the upper wiring is substantially coplanar with a top surface of the second interlayer insulating layer, a bottom surface of the second portion of the upper wiring contacts a top surface of the first portion of the upper wiring and the second interlayer insulating layer, a width of the bottom surface of second portion of the upper wiring is greater than a width of the top surface of first portion of the upper wiring. ### Claim 40 (depends on 39) The semiconductor device of claim 39, wherein the lower wiring includes copper, and the second portion of the upper wiring includes aluminum.