# US 2021/0242074 A1 · Selective deposition of conductive cap for fully-aligned-via (fav)

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- Number: US 2021/0242074 A1
- Document ID: US20210242074A1
- Status: Published application
- Kind: A1
- Application number: 16/782,344
- Filed: 2020-02-05
- Published: 2021-08-05
- Earliest claimed: 2020-02-05
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: Yen-Tien Lu; Kai-Hung Yu; Xinghua Sun; Angelique Raley
- Web page: https://patentgrep.com/patent/US20210242074A1

## CPC

- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H}
- H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 50/283: {by chemical means}
- H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3}
- H10P 72/0421: {for drying etching}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

## Claims

### Claim 1

A method for processing a substrate, comprising:
receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material;
forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material;
forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer; and
selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second conductive material comprises ruthenium (Ru).

### Claim 3 (depends on 1)

The method of claim 1, wherein the cap is formed to a thickness in a range of 5-10 nm

### Claim 4 (depends on 1)

The method of claim 1, wherein the etch stop layer comprises a dielectric material.

### Claim 5 (depends on 4)

The method of claim 4, wherein the dielectric material SiCN.

### Claim 6 (depends on 4)

The method of claim 4, wherein the dielectric material comprises SiOC.

### Claim 7 (depends on 4)

The method of claim 4, wherein the dielectric material comprises AlO.

### Claim 8 (depends on 4)

The method of claim 4, wherein the dielectric material comprises AlN.

### Claim 9 (depends on 1)

The method of claim 1, wherein the etch stop layer is deposited to a thickness in a range of 2-10 nm.

### Claim 10 (depends on 1)

The method of claim 1, wherein the plasma etch process comprises filling a plasma etch chamber with a mixture of etch gasses comprising one or more of CF4, CHF3, CH2F2, CH3F, CH4, C4F6, C4F8, BCl3.

### Claim 11 (depends on 10)

The method of claim 10, wherein the etch gas is provided to the plasma etch chamber at a flow rate in a range of 0-100 sccm for each gas.

### Claim 12 (depends on 10)

The method of claim 10, wherein the plasma etch chamber is operated at a pressure in a range of 10-100 mTorr.

### Claim 13 (depends on 10)

The method of claim 10, wherein the plasma etch chamber is operated at a temperature in a range of 20-60° C.

### Claim 14 (depends on 10)

The method of claim 10, wherein the plasma etch chamber is operated at a high frequency power level in a range of 0-1200 W.

### Claim 15 (depends on 10)

The method of claim 10, wherein the plasma etch chamber is operated at a low frequency power level in a range of 0-1200 W.

### Claim 16 (depends on 1)

The method of claim 1, further comprising forming a plurality of layers on the etch stop layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the plurality of layers comprises at least one patterned layer, the patterned layer defining a region for forming a via to contact the cap.

### Claim 18 (depends on 17)

The method of claim 17, wherein the plurality of layers is etched expose the etch stop layer in the region defined by the patterned layer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming a conductive via structure in contact with the cap.

### Claim 20

A system for processing a substrate, comprising:
a processing chamber configured to receive the substrate having a multi-line layer formed thereon, the multi-line layer including a region having a pattern of alternating lines of a plurality of materials, wherein each line has a horizontal thickness, a vertical height, and extends horizontally across an underlying layer, wherein each line of the pattern of alternating lines extends vertically from a top surface of the multi-line layer to a bottom surface of the multi-line layer; and
a controller coupled to the processing chamber and configured to control operations of the processing chamber to cause the processing chamber to:
form a patterned recess in the multi-line layer to expose at least a first component of the multi-line layer and a second component of the multi-line layer; and
etch the first component with a non-corrosive etch process that is selective to the second component.