# US 2021/0242072 A1 · Three dimensional memory device and method for fabricating the same

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- Number: US 2021/0242072 A1
- Document ID: US20210242072A1
- Status: Published application
- Kind: A1
- Application number: 16/782,093
- Filed: 2020-02-05
- Published: 2021-08-05
- Earliest claimed: 2020-02-05
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Erh-Kun LAI; Hsiang-Lan LUNG
- Web page: https://patentgrep.com/patent/US20210242072A1

## CPC

- H10W 10/20: Air gaps
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 50/283: {by chemical means}
- H10W 10/021: {of air gaps}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/43: Layouts of interconnections
- H10W 20/46: comprising air gaps
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional memory device includes a substrate, a plurality of horizontal conductive layers, a plurality of vertical memory structures and a vertical conductive post. The conductive layers are located above the substrate, and immediately-adjacent two of the conductive layers are spaced by a first air gap. The memory structures pass through the conductive layers and are connected to the substrate. The conductive post is located between immediately-adjacent two of the memory structures and passes through the conductive layers and is connected to the substrate. The conductive post is spaced from immediately-adjacent edges of the conductive layers by a second air gap.

## Claims

### Claim 1

A three-dimensional (3D) memory device, comprising:
a substrate;
a plurality of horizontal conductive layers disposed above the substrate, immediately-adjacent two of the conductive layers are spaced by a first air gap;
a plurality of vertical memory structures passing through the conductive layers and connected to the substrate; and
a vertical conductive post disposed between immediately-adjacent two of the memory structures and passing through the conductive layers and connected to the substrate, the conductive post is spaced from immediately-adjacent edges of the conductive layers by a second air gap.

### Claim 2 (depends on 1)

The 3D memory device of claim 1, wherein the first air gap fluidly communicates with the second air gap.

### Claim 3 (depends on 1)

The 3D memory device of claim 1 further comprising a conformal oxide layer formed over surfaces of the conductive layers, the memory structures and the conductive post that are exposed to the first and second air gaps.

### Claim 4 (depends on 3)

The 3D memory device of claim 3, wherein the oxide layer has a uniform thickness ranging from about 1 nm to about 5 nm.

### Claim 5 (depends on 1)

The 3D memory device of claim 1, wherein each memory structure comprises a storage layer in contact with the conductive layers and a channel layer in contact with the storage layer.

### Claim 6 (depends on 1)

The 3D memory device of claim 1, wherein the first air gap has a width ranging from about 10 nm to about 50 nm.

### Claim 7 (depends on 1)

The 3D memory device of claim 1, wherein the first air gap has a width that is smaller than about 20 nm.

### Claim 8 (depends on 1)

The 3D memory device of claim 1, wherein the second air gap has a width ranging from about 10 nm to about 100 nm.

### Claim 9 (depends on 1)

The 3D memory device of claim 1, wherein the second air gap has a width that is smaller than about 50 nm.

### Claim 10 (depends on 1)

The 3D memory device of claim 1, further comprising a non-conformal layer disposed over top portions of the conductive layers, the memory structures and the conductive post.

### Claim 11 (depends on 10)

The 3D memory device of claim 10, wherein the non-conformal layer has a third air gap disposed between the conductive post and an immediately-adjacent one of the memory structures.

### Claim 12 (depends on 11)

The 3D memory device of claim 11, wherein the third air gap does not fluidly communicate with the first and second air gaps.

### Claim 13 (depends on 1)

The 3D memory device of claim 1, further comprising a non-conformal layer disposed over top portions of the memory structures and the conductive post, a third air gap is formed under the non-conformal layer and between the conductive post and an immediately-adjacent one of the memory structures.

### Claim 14 (depends on 13)

The 3D memory device of claim 13, wherein the third air gap fluidly communicates with the first and second air gaps.

### Claim 15

A method for fabricating a three-dimensional memory device comprising:
alternately depositing multiple first insulating layers and second insulating layers over a substrate;
etching first holes through the first and second insulating layers;
forming vertical memory structures in the first holes;
etching a trench between immediately-adjacent two of the memory structures;
etching the first insulating layers via the trench to form voids between the second insulating layers;
depositing a conductive material into the voids via the trench to form horizontal conductive layers between the second insulating layers;
depositing a third insulating layer over a sidewall of the trench;
depositing a vertical conductive post into the trench and within the third insulating layer; and
removing the second insulating layers and the third insulating layer to form a first air gap between immediately-adjacent two of the conductive layers and a second air gap between the conductive post and immediately-adjacent edges of the conductive layers.

### Claim 16 (depends on 15)

The method of claim 15 further comprising depositing a conformal oxide layer over surfaces of the conductive layers, the memory structures and the conductive post that are exposed to the first and second air gaps.

### Claim 17 (depends on 15)

The method of claim 15 further comprising depositing a non-conformal layer disposed over top portions of the conductive layers, the memory structures and the conductive post.

### Claim 18 (depends on 17)

The method of claim 17, wherein the non-conformal layer has a third air gap disposed between the conductive post and an immediately-adjacent one of the memory structures.

### Claim 19 (depends on 18)

The method of claim 18, wherein the third air gap does not fluidly communicate with the first and second air gaps.

### Claim 20 (depends on 15)

The method of claim 15, wherein the first air gap fluidly communicates with the second air gap.