# US 2021/0242050 A1 · Semiconductor device having hybrid bonding interface, method of manufacturing the semiconductor device, and method of manufacturing semiconductor device assembly

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0242050 A1
- Document ID: US20210242050A1
- Status: Published application
- Kind: A1
- Application number: 16/781,377
- Filed: 2020-02-04
- Published: 2021-08-05
- Earliest claimed: 2020-02-04
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Hsih-Yang CHIU
- Web page: https://patentgrep.com/patent/US20210242050A1

## CPC

- H10P 72/0438: {Apparatus for making assemblies not otherwise provided for, e.g. package constructions}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10P 72/0418: {for etching}
- H10W 20/43: Layouts of interconnections
- H10W 72/013: {of die-attach connectors}
- H10W 72/90: Bond pads, in general
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10W 72/019: {of bond pads}
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/01955: {by using masks}
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/168: {using guiding structures}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/334: {Thermocompression bonding}
- H10W 80/732: {having shape changed during the connecting}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/792: {between multiple chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor device, a method of manufacturing the semiconductor device and a mothed of method of manufacturing a semiconductor device assembly. The semiconductor device includes a substrate, a bonding dielectric disposed on the substrate, a first conductive feature disposed in the bonding dielectric, an air gap disposed in the bonding dielectric to separate a portion of a periphery of the first conductive feature from the bonding dielectric, and a second conductive feature including a base disposed in the bonding dielectric and a protrusion stacked on the base.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a bonding dielectric disposed on the substrate;
at least one first conductive feature disposed in the bonding dielectric;
at least one air gap disposed in the bonding dielectric to separate a portion of a periphery of the first conductive feature from the bonding dielectric; and
at least one second conductive feature comprising a base disposed in the bonding dielectric and a protrusion stacked on the base.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the air gap has a first width, and the protrusion of the second conductive feature has a second width less than the first width.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the base of the second conductive feature has a third width, and the first conductive feature has a fourth width less than the third width.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the third width is equal to a sum of the first width and the fourth width.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second conductive feature has an L-shaped contour.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a plurality of diffusion barrier liners disposed between the bonding dielectric and the first conductive feature and between the bonding dielectric and the base.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first conductive feature and the second conductive feature penetrate through the bonding dielectric and contact the substrate.

### Claim 8

A method of manufacturing a semiconductor device, comprising:
forming a dielectric layer on a substrate;
etching the dielectric layer to create a plurality of openings in the dielectric layer;
applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer;
forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed;
removing the sacrificial layer to form at least one air gap in the dielectric layer; and
forming a plurality of protrusions on the bases.

### Claim 9 (depends on 8)

The method of claim 8, wherein in a pair of openings, only a portion of the dielectric layer is covered by the sacrificial layer.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first conductive feature and the bases are arranged in an interleaved configuration.

### Claim 11 (depends on 8)

The method of claim 8, wherein the first conductive feature and the bases are formed using a plating process.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first conductive feature, the bases and the protrusions have the same material.

### Claim 13 (depends on 8)

The method of claim 8, wherein the formation of the protrusions comprises:
applying a patterned mask comprising a plurality of through holes on the dielectric layer, the first conductive feature and the bases, wherein portions of the bases are exposed through the through holes; and
performing a plating process to deposit a conductive material in the through holes.

### Claim 14 (depends on 8)

The method of claim 8, further comprising:
depositing a diffusion barrier layer in the openings before the applying of the sacrificial layer in the openings; and
removing portions of the diffusion barrier layer not covered by the first conductive feature and the base after the formation of the protrusions.

### Claim 15

A method of manufacturing a semiconductor device assembly, comprising:
providing a pair of semiconductor devices comprising at least one first conductive feature and at least one second conductive feature having complimentary structures;
aligning the semiconductor devices to cause the first conductive feature of one of the semiconductor devices to be in contact with the second conductive feature of the other semiconductor device; and
performing an annealing process to bond the first conductive feature to the second conductive feature.

### Claim 16 (depends on 15)

The method of claim 15, wherein the semiconductor devices comprise a bonding dielectric covering a portion of a periphery of the first conductive feature and enclosing the second conductive feature, wherein the bonding dielectrics are fused during the performing of the annealing process.

### Claim 17 (depends on 15)

The method of claim 15, wherein a void is introduced between the first and second conductive features after the alignment of the semiconductor devices.

### Claim 18 (depends on 17)

The method of claim 17, wherein the void is eliminated after the performing of the annealing process due to the thermal expansion of the first and second conductive features.

### Claim 19 (depends on 15)

The method of claim 15, wherein the connected first and second conductive features serve as an electrical interconnection to the semiconductor devices.

### Claim 20 (depends on 15)

The method of claim 15, wherein the semiconductor device comprises a plurality of first conductive features and a plurality of second conductive features arranged in an interleaved configuration.