# US 2021/0242037 A1 · Method for fabricating semiconductor interconnect structure and semiconductor structure thereof

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- Number: US 2021/0242037 A1
- Document ID: US20210242037A1
- Status: Published application
- Kind: A1
- Application number: 17/236,933
- Filed: 2021-04-21
- Published: 2021-08-05
- Earliest claimed: 2018-11-30
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Pingheng WU
- Web page: https://patentgrep.com/patent/US20210242037A1

## CPC

- H10W 70/095: {of vias therein}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/2125: {Top-view shapes}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor interconnect structure and a fabricating method thereof are disclosed. The method comprises: providing a stacked structure comprising bonded multiple layers of wafer or die, each bonded layer comprises a substrate and a wiring layer, and the wiring layer comprises metal wires; vertically forming, in the stacked structure, a first blind hole having a first diameter and a first length and penetrating each bonded layer between adjacent metal wires, the first diameter is less than a space between the adjacent metal wires, and the first length is less than a height of the stacked structure; forming a second blind hole having a second diameter and the first length coaxially with the first blind hole, a sidewall of the second blind hole exposes the metal wires, and the second diameter is larger than the space between the adjacent metal wires; and filling a conductive material in the second blind hole.

## Claims

### Claim 1

A method for fabricating a semiconductor interconnect structure, comprising:
providing a stacked structure comprising bonded a plurality of layers of wafer or die, wherein each layer of wafer or die comprises a substrate and a wiring layer, and the wiring layer comprises a plurality of metal wires;
vertically forming, in the stacked structure, a first blind hole having a first diameter and a first length, wherein a penetration position of the first blind hole in each layer of wafer or die is between adjacent metal wires, the first diameter is less than a space between the adjacent metal wires, and the first length is less than a height of the stacked structure;
forming a second blind hole having a second diameter and the first length coaxially with the first blind hole, wherein a sidewall of the second blind hole exposes end surfaces of the plurality of metal wires, and the second diameter is larger than the space between the adjacent metal wires; and
filling a conductive material in the second blind hole.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the second blind hole having the second diameter and the first length coaxially with the first blind hole comprises:
widening a portion of the first blind hole in the substrate of each layer of wafer or die to the second diameter by a first wet etch process; and
extending, by a second wet etching process, a portion of the first blind hole in the wiring layer of each layer of wafer or die to the second diameter to expose the end surfaces of the plurality of metal wires to form the second blind hole.

### Claim 3 (depends on 2)

The method of claim 2, wherein filling the conductive material in the second blind hole comprises:
forming a dielectric isolation layer on an inner surface of the second blind hole; and
etching the dielectric isolation layer to expose the end surfaces of the plurality of metal wires and a bottom of the second blind hole.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the dielectric isolation layer comprises depositing SiCN on the inner surface of the second blind hole by a chemical vapor deposition process.

### Claim 5 (depends on 3)

The method of claim 3, wherein etching the dielectric isolation layer to expose the end surfaces of the plurality of metal wires and the bottom of the second blind hole comprises:
etching, by a plasma dry etch process, portions of the dielectric isolation layer on the end surfaces and upper surfaces of the plurality of metal wires to expose the plurality of metal wires, and etching a portion of the dielectric isolation layer at the bottom of the second blind hole to expose the bottom of the second blind hole.

### Claim 6 (depends on 5)

The method of claim 5, wherein filling the conductive material in the second blind hole comprises:
sputtering a seed metal on the etched dielectric isolation layer and the exposed end surfaces of the plurality of metal wires and the bottom of the second blind hole, wherein the seed metal comprises tantalum or copper; and
growing the conductive metal in the second blind holes sputtered with the seed metal, the conductive metal comprises copper.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
grinding a bottom layer of the stacked structure to expose a metal filled at a bottom of the second blind hole; and
forming a bump on a surface of the exposed metal.

### Claim 8 (depends on 1)

The method of claim 1, wherein each of the first blind hole and the second blind hole has a cross-sectional top view of a circle shape, a polygon shape, and an irregular shape.

### Claim 9 (depends on 1)

The method of claim 1, wherein the plurality of layers of wafer or die are directly bonded, wherein a substrate of a top layer is directly disposed on a wiring layer of a lower layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein
a difference between the first diameter and the space between the adjacent metal wires is within a first preset safe range, and
a difference between the second diameter and the space between the adjacent metal wires is within a second preset safe range.

### Claim 11

A semiconductor interconnect structure, comprising:
a stacked structure comprising bonded a plurality of layers of wafer or die, each layer of wafer or die comprising a substrate and a wiring layer, and the wiring layer comprising a plurality of metal wires; and
at least a through silicon via (TSV) penetrating the bonded plurality of layers of wafer or die of the stacked structure, a center of a penetration position on each layer of wafer or die being located between adjacent metal wires, and a sidewall of the through silicon via intersecting with the plurality of metal wires,
wherein the through silicon via penetrating the bonded plurality of layers of wafer or die of the stacked structure is fabricated by a process including one single etching process.

### Claim 12 (depends on 11)

The semiconductor interconnect structure of claim 11, wherein the through silicon via has a cross-sectional top view of a circle shape, a polygon shape, or an irregular shape.

### Claim 13 (depends on 11)

The semiconductor interconnect structure of claim 11, wherein the through silicon via penetrating the bonded plurality of layers of wafer or die is a one-piece structure formed integrally.

### Claim 14 (depends on 11)

The semiconductor interconnect structure of claim 11, wherein the through silicon via penetrating the bonded plurality of layers of wafer or die comprises no bumps among the bonded plurality of layers of wafer or die.

### Claim 15 (depends on 11)

The semiconductor interconnect structure of claim 11, wherein a difference between a diameter of the through silicon via and a space between the adjacent metal wires is within a preset safe range.

### Claim 16 (depends on 15)

The semiconductor interconnect structure of claim 15, wherein the diameter of the through silicon via is consistent in each of the bonded plurality of layers of wafer or die.

### Claim 17 (depends on 11)

The semiconductor interconnect structure of claim 11, wherein a dielectric isolation layer is disposed on an inner surface of the through silicon via, and the dielectric isolation layer exposes end surfaces of the plurality of metal wires.

### Claim 18 (depends on 17)

The semiconductor interconnect structure of claim 17, wherein a seed metal is sputtered on the dielectric isolation layer and the exposed end surfaces of the plurality of metal wires, and the seed metal comprises tantalum or copper.

### Claim 19 (depends on 18)

The semiconductor interconnect structure of claim 18, wherein the through silicon via is filled with a conductive metal, and the conductive metal comprises copper.

### Claim 20

A semiconductor structure, including a semiconductor interconnect structure fabricated by a method, wherein the method comprises:
providing a stacked structure comprising bonded a plurality of layers of wafer or die, wherein each layer of wafer or die comprises a substrate and a wiring layer, and the wiring layer comprises a plurality of metal wires;
vertically forming, in the stacked structure, a first blind hole having a first diameter and a first length, wherein a penetration position of the first blind hole in each layer of wafer or die is between adjacent metal wires, the first diameter is less than a space between the adjacent metal wires, and the first length is less than a height of the stacked structure;
forming a second blind hole having a second diameter and the first length coaxially with the first blind hole, wherein a sidewall of the second blind hole exposes end surfaces of the plurality of metal wires, and the second diameter is larger than the space between the adjacent metal wires; and
filling a conductive material in the second blind hole.