# US 2021/0242034 A1 · Sintering method using a sacrificial layer on the backside metallization of a semiconductor die

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- Number: US 2021/0242034 A1
- Document ID: US20210242034A1
- Status: Published application
- Kind: A1
- Application number: 17/167,620
- Filed: 2021-02-04
- Published: 2021-08-05
- Earliest claimed: 2020-02-05
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Frederik OTTO; Paul FRANK
- Web page: https://patentgrep.com/patent/US20210242034A1

## CPC

- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 72/073: {of die-attach connectors}
- H10W 74/01: Manufacture or treatment
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 72/019: {of bond pads}
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07341: {Controlling the bonding environment, e.g. atmosphere composition or temperature}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic device comprises a semiconductor die, a layer stack disposed on the semiconductor die and comprising one or more functional layers, wherein the layer stack comprises a protection layer which is an outermost functional layer of the layer stack, and a sacrificial layer disposed on the protection layer, wherein the sacrificial layer comprises a material which decomposes or becomes volatile at a temperature between 100° and 400° C.

## Claims

### Claim 1

An electronic device, comprising:
a semiconductor die;
a layer stack disposed on the semiconductor die (and comprising one or more functional layers, wherein the layer stack comprises a protection layer which is an outermost functional layer of the layer stack; and
a sacrificial layer disposed on the protection layer, wherein the sacrificial layer comprises a material which decomposes or becomes volatile at a temperature between 100° and 400° C.

### Claim 2 (depends on 1)

The electronic device according to claim 1, wherein
the material of the sacrificial layer comprises carbon.

### Claim 3 (depends on 2)

The electronic device according to claim 2, wherein
a thickness of the sacrificial layer is in a range from 0.1 nm or monolayer thickness up to 200 nm.

### Claim 4 (depends on 1)

The electronic device according to claim 1, wherein
the material of the sacrificial layer comprises a metal.

### Claim 5 (depends on 1)

The electronic device according to claim 1, wherein
the material of the sacrificial layer comprises one or more of organic molecules and/or fatty acids.

### Claim 6 (depends on 5)

The electronic device according to claim 5, wherein
a thickness of the sacrificial layer is in a range from 0.1 to 10 nm.

### Claim 7 (depends on 1)

The electronic device according to claim 1, wherein
the protection layer comprises Ag.

### Claim 8 (depends on 1)

The electronic device according to claim 1, wherein
the layer stack comprises four layers.

### Claim 9 (depends on 8)

The electronic device according to claim 8, wherein
the layer stack comprises the following layer sequence following the semiconductor die: an Al layer, a Ti layer, a layer comprising Ni, and an Ag layer.

### Claim 10

A method for fabricating an electronic device, the method comprising:
providing a semiconductor die;
disposing a layer stack on the semiconductor die, the layer stack comprising one or more functional layers, wherein the layer stack comprises a protection layer which is an outermost functional layer of the layer stack; and
disposing a sacrificial layer on the protection layer, wherein the sacrificial layer comprises a material which decomposes or becomes volatile at a temperature between 100° and 400° C.

### Claim 11 (depends on 10)

The method according to claim 10, wherein
the material of the sacrificial layer comprises carbon.

### Claim 12 (depends on 11)

The method according to claim 11, wherein
a thickness of the sacrificial layer is in a range from 0.1 nm or monolayer thickness to 200 nm.

### Claim 13 (depends on 10)

The method according to claim 10, wherein
the material of the sacrificial layer comprises a metal.

### Claim 14 (depends on 10)

The method according to claim 10, wherein
the material of the sacrificial layer comprises one or more of organic molecules and/or fatty acids.

### Claim 15 (depends on 14)

The method according to claim 14, wherein
a thickness of the sacrificial layer is in a range from 0.1 to 10 nm.

### Claim 16 (depends on 1)

The method according to claim 1, comprising disposing the sacrificial layer on the protection layer by foil-assisted application.

### Claim 17

A method for fabricating an electronic module, the method comprising:
providing a carrier;
providing an electronic device comprising a semiconductor die, a layer stack comprising disposed on the semiconductor die and comprising one or more functional layers, wherein the layer stack comprises a protection layer which is an outermost functional layer of the layer stack, and a sacrificial layer disposed on the protection layer, wherein the sacrificial layer comprises a material which itself decomposes or becomes volatile at a temperature between 100° and 400° C. or which decomposes or becomes volatile at a temperature between 100° C. and 400° C. when or after reacting with oxygen or oxygen compounds;
applying a sinter paste to a main surface of the carrier; and
sintering the electronic device onto the carrier at a temperature between 100° C. and 400° C. in such a way that the sacrificial layer itself is completely decomposed or becomes volatile or which decomposes or becomes volatile at a temperature between 100° C. and 400° C. when or after reacting with oxygen or oxygen compounds.

### Claim 18 (depends on 17)

The method according to claim 17, wherein
the carrier comprises one or more of a portion of a leadframe, a direct copper bond (DCB), an active metal braze (AMB), or an isolated metal substrate (IMS).

### Claim 19 (depends on 17)

The method according to claim 17, wherein
sintering is carried out at a temperature in a range from 150° C. to 350° C.

### Claim 20 (depends on 19)

The method according to claim 19, wherein
sintering is carried out at a temperature in a range from 200° C. to 300° C.