# US 2021/0242033 A1 · Gate electrode and method for manufacturing the same, and method for manufacturing array substrate

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0242033 A1
- Document ID: US20210242033A1
- Status: Published application
- Kind: A1
- Application number: 16/303,959
- Filed: 2018-05-23
- Published: 2021-08-05
- Earliest claimed: 2017-05-26
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Bin ZHANG; Chienhung LIU; Yucheng CHAN; Xuefei SUN; Tingting ZHOU
- Web page: https://patentgrep.com/patent/US20210242033A1

## CPC

- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 64/01: Manufacture or treatment
- H10D 64/517: {characterised by the conducting layers}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/3456: {Polycrystalline}
- H10P 14/6314: {of a metallic layer}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A gate electrode and a method for manufacturing the same, and a method for manufacturing an array substrate are provided. The method for manufacturing a gate electrode may include: providing a substrate, wherein the substrate includes a gate electrode region and a non-gate electrode region; and forming a gate electrode layer on the substrate, wherein the gate electrode layer includes a conductive portion corresponding to the gate electrode region and a transparent portion corresponding to the non-gate electrode region. According to the gate electrode and the method for manufacturing the same, and the method for manufacturing an array substrate, step difference can be eliminated, thereby avoiding an influence of the step difference on the crystallization property of a polysilicon material when an Excimer Laser Annealing (ELA) process is performed on the amorphous silicon layer, and obtaining a better crystallization effect.

## Claims

### Claim 1

A method for manufacturing a gate electrode, comprising:
a step S1 of providing a substrate, the substrate comprising a gate electrode region and a non-gate electrode region; and
a step S2 of forming a gate electrode layer on the substrate, the gate electrode layer comprising a conductive portion corresponding to the gate electrode region and a transparent portion corresponding to the non-gate electrode region,
wherein the conductive portion has a thickness equal to a thickness of the transparent portion.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the step S2 further comprises:
a step S21 of forming a metal material layer on the substrate;
a step S22 of forming a patterned mask layer on the metal material layer, so that a portion of the metal material layer corresponding to the gate electrode region is covered by the patterned mask layer; and
a step S23 of oxidizing a portion of the metal material layer corresponding to the non-gate electrode region to a transparent oxide layer by oxidizing the portion of the metal material layer corresponding to the non-gate electrode region.

### Claim 3 (depends on 2)

The method according to claim 2, wherein
the metal material layer is a metal layer of tantalum, and
the transparent oxide layer is a transparent layer of tantalum oxide.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the transparent layer of tantalum oxide contains tantalum trioxide or tantalum pentoxide.

### Claim 5 (depends on 2)

The method according to claim 2, wherein the step S22 further comprises:
a step S221 of forming a mask layer on an entire surface of the metal material layer; and
a step S222 of patterning the mask layer by performing a photolithography process on the mask layer so as to form the patterned mask layer.

### Claim 6 (depends on 1)

A method for manufacturing an array substrate, comprising:
a step S100 of forming the gate electrode layer on the substrate by using the method of claim 1.

### Claim 7 (depends on 6)

The method according to claim 6, after the step S100, further comprising:
a step S200 of forming a gate insulating layer on the gate electrode layer and forming an active layer on the gate insulating layer.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the step S200 further comprises:
a step S201 of forming the gate insulating layer on the gate electrode layer;
a step S202 of forming an amorphous silicon layer on the gate insulating layer; and
a step S203 of converting the amorphous silicon layer into a polysilicon layer served as the active layer by performing an Excimer Laser Annealing (ELA) process on the amorphous silicon layer.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the gate insulating layer and the amorphous silicon layer are formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) process.

### Claim 10

A gate electrode, comprising: a gate electrode layer disposed on a substrate, wherein the substrate comprises a gate electrode region and a non-gate electrode region;
the gate electrode layer comprises a conductive portion corresponding to the gate electrode region and a transparent portion corresponding to the non-gate electrode region, and the conductive portion has a thickness equal to a thickness of the transparent portion.

### Claim 11 (depends on 2)

A method for manufacturing an array substrate, comprising:
a step S100 of forming the gate electrode layer on the substrate by using the method of claim 2.

### Claim 12 (depends on 11)

The method according to claim 11, after the step S100, further comprising:
a step S200 of forming a gate insulating layer on the gate electrode layer and forming an active layer on the gate insulating layer.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the step S200 further comprises:
a step S201 of forming the gate insulating layer on the gate electrode layer;
a step S202 of forming an amorphous silicon layer on the gate insulating layer; and
a step S203 of converting the amorphous silicon layer into a polysilicon layer served as the active layer by performing an Excimer Laser Annealing (ELA) process on the amorphous silicon layer.

### Claim 14 (depends on 5)

A method for manufacturing an array substrate, comprising:
a step S100 of forming the gate electrode layer on the substrate by using the method of claim 5.

### Claim 15 (depends on 14)

The method according to claim 14, after the step S100, further comprising:
a step S200 of forming a gate insulating layer on the gate electrode layer and forming an active layer on the gate insulating layer.

### Claim 16 (depends on 15)

The method according to claim 15, wherein the step S200 further comprises:
a step S201 of forming the gate insulating layer on the gate electrode layer;
a step S202 of forming an amorphous silicon layer on the gate insulating layer; and
a step S203 of converting the amorphous silicon layer into a polysilicon layer served as the active layer by performing an Excimer Laser Annealing (ELA) process on the amorphous silicon layer.