# US 2021/0242025 A1 · Silicidation of source/drain region of vertical field effect transistor (vfet) structure

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- Number: US 2021/0242025 A1
- Document ID: US20210242025A1
- Status: Published application
- Kind: A1
- Application number: 17/026,532
- Filed: 2020-09-21
- Published: 2021-08-05
- Earliest claimed: 2020-02-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Min Gyu Kim; Hwi Chan Jun
- Web page: https://patentgrep.com/patent/US20210242025A1

## CPC

- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A vertical field effect transistor (VFET) structure includes: a substrate; fin structures formed on the substrate; bottom source/drain regions formed on the substrate between and at opposite sides of lower portions of the fin structures; and shallow trench isolation (STI) structures formed at sides of the substrate and the bottom source/drain regions, wherein upper portions of the bottom source/drain regions include silicide layers each of which has a bar shape.

## Claims

### Claim 1

A vertical field effect transistor (VFET) structure comprising:
a substrate;
fin structures formed on the substrate;
bottom source/drain regions formed on the substrate between and at opposite sides of lower portions of the fin structures; and
shallow trench isolation (STI) structures formed at sides of the substrate and the bottom source/drain regions,
wherein upper portions of the bottom source/drain regions comprise bottom silicide layers each of which has a bar shape.

### Claim 2 (depends on 1)

The VFET structure of claim 1, wherein the bottom source/drain regions comprise:
a first bottom source/drain region formed on the substrate between the lower portions of the fin structures; and
a second bottom source/drain region formed on the substrate at a left side of a lower portion of one of the fin structures, and
wherein a top surface of an upper portion of the second bottom source/drain region comprising one of the bottom silicide layers is substantially coplanar with a top surface of one of the STI structures facing the substrate and the second bottom source/drain region.

### Claim 3 (depends on 2)

The VFET structure of claim 2, wherein the bottom source/drain regions further comprising a third bottom source/drain region formed on the substrate and at a right side of a lower portion of another one of the fin structures, and
wherein a top surface of an upper portion of the third bottom source/drain region comprising another one of the bottom silicide layers is substantially coplanar with a top surface of another one of the STI structures facing the substrate and the third bottom source/drain region.

### Claim 4 (depends on 1)

The VFET structure of claim 1, wherein top surfaces of the STI structures and top surfaces of the upper portions of the bottom source/drain regions are substantially coplanar with one another.

### Claim 5 (depends on 1)

The VFET structure of claim 1, wherein each of the bottom silicide layers is formed of at least one of cobalt silicide (CoSix), titanium silicide (TiSix) or tungsten silicide (WSix).

### Claim 6 (depends on 1)

The VFET structure of claim 1, further comprising top source/drain regions formed on the fin structures, respectively,
wherein upper portions of the top source/drain regions comprise top silicide layers, respectively.

### Claim 7 (depends on 6)

The VFET structure of claim 6, further comprising interlayer dielectric (ILD) layers between and at sides of the fin structures,
wherein portions of the top source/drain regions are protruded from the ILD layers, and
wherein the top silicide layers cover substantially all outer surfaces of the top source/drain region protruded from the ILD layers.

### Claim 8 (depends on 6)

The VFET structure of claim 6, wherein each of the top silicide layers is formed of at least one of cobalt silicide (CoSix), titanium silicide (TiSix) and tungsten silicide (WSix).

### Claim 9

A vertical field effect transistor (VFET) structure comprising:
a substrate;
fin structures formed on the substrate;
bottom source/drain regions formed on the substrate between and at opposite sides of lower portions of the fin structures;
shallow trench isolation (STI) structures formed at sides of the substrate and the bottom source/drain regions; and
top source/drain regions formed on the fin structures, respectively,
wherein upper portions of the top source/drain regions comprise top silicide layers, respectively.

### Claim 10 (depends on 9)

The VFET structure of claim 9, further comprising interlayer dielectric (ILD) layers between and at sides of the fin structures,
wherein portions of the top source/drain regions are protruded from the ILD layers, and
wherein the top silicide layers cover substantially all outer surfaces of the top source/drain region protruded from the ILD layers.

### Claim 11 (depends on 10)

The VFET structure of claim 10, wherein upper portions of the bottom source/drain regions comprise bottom silicide layers each of which has a bar shape.

### Claim 12 (depends on 11)

The VFET structure of claim 11, wherein each of the bottom and top silicide layers is formed of at least one of cobalt silicide (CoSix), titanium silicide (TiSix) and tungsten silicide (WSix).

### Claim 13

A method for manufacturing a vertical field effect transistor (VFET) structure, the method comprising:
providing an intermediate VFET structure comprising a substrate, and fin structures and bottom source/drain regions on the substrate at opposite sides of lower portions of the fin structures;
siliciding upper portions of the bottom source/drain regions so that bottom silicide layers are formed at upper portions of the bottom source/drain regions; and
forming shallow trench isolation (STI) structures at sides of the substrate and the bottom source/drain regions of which the upper portions are silicided,
wherein each of the bottom silicide layers has a bar shape.

### Claim 14 (depends on 13)

The method of claim 13, wherein the siliciding the upper portions of the bottom source/drain regions comprises:
forming a metal layer on top and side surfaces of the fin structures and top surfaces of the bottom source/drain regions;
annealing the metal layer at predetermined high temperature so that the metal layer at the upper portions of the bottom source/drain regions change to the bottom silicide layers; and
removing the metal layer from the top and side surfaces of the fin structures.

### Claim 15 (depends on 14)

The method of claim 14, wherein the metal layer comprises at least one of cobalt, titanium and tungsten.

### Claim 16 (depends on 14)

The method of claim 14, wherein the siliciding the upper portions of the bottom source/drain regions comprises:
forming protection layers on the side surfaces of the fin structures before the metal layer is formed on the top and side surfaces of the fin structures so that the metal layer formed on the side surfaces of the fin structures is formed on side surfaces of the protection layers; and
removing the protection layers with the metal layer from the side surfaces of the fin structures after the metal layer is annealed.

### Claim 17 (depends on 13)

The method of claim 13, wherein the forming the STI structures is performed such that top surfaces of the STI structures and top surfaces of the upper portions of the bottom source/drain regions are substantially coplanar with one another.

### Claim 18 (depends on 13)

The method of claim 13, further comprising:
forming top source/drain regions on the fin structures, respectively;
forming interlayer dielectric (ILD) layers between and at sides of the fin structures; and
siliciding upper portions of the top source/drain region so that top silicide layers are formed at the upper portions of the top source/drain regions, respectively.

### Claim 19 (depends on 18)

The method of claim 18, wherein the siliciding the upper portions of the top source/drain regions comprises:
forming a metal layer on top surfaces of the top source/drain regions protruded from the ILD layers and top surfaces of the ILD layers;
annealing the metal layer; and
removing the metal layer from the top surfaces of the ILD layers,
wherein the metal layer comprises at least one of cobalt, titanium and tungsten.

### Claim 20 (depends on 18)

The method of claim 18, wherein the siliciding the upper portions of the top source/drain regions is performed such that the top silicide layers are formed on substantially all outer surfaces of the top source/drain regions protruded from the ILD layers.