# US 2021/0242024 A1 · Mask layout, semiconductor device and manufacturing method using the same

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- Number: US 2021/0242024 A1
- Document ID: US20210242024A1
- Status: Published application
- Kind: A1
- Application number: 17/233,970
- Filed: 2021-04-19
- Published: 2021-08-05
- Earliest claimed: 2019-03-29
- Assignees: MagnaChip Semiconductor, Ltd.
- Applicants: MagnaChip Semiconductor, Ltd.
- Inventors: Guk Hwan KIM
- Web page: https://patentgrep.com/patent/US20210242024A1

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 89/10: Integrated device layouts
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a gate insulating film on a substrate;
forming a gate electrode on the gate insulating film;
forming a source region and a drain region on both ends of the gate electrode;
forming a first insulating film on the gate electrode, the source region, and the drain region;
forming a silicide blocking film on the gate electrode, the source region, and the drain region by patterning the first insulating film; and
forming a silicide film on the gate electrode, a portion of the source region, and a portion of the drain region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the silicide blocking film is formed by extending from the gate electrode to the source and drain regions.

### Claim 3 (depends on 1)

The method of claim 1, wherein a gate electrode mask pattern is disposed to overlap an active mask pattern to form the gate electrode between the source region and the drain region.

### Claim 4 (depends on 3)

The method of claim 3, wherein the active mask pattern is used to form the source region and the drain region on both ends of the gate electrode.

### Claim 5 (depends on 4)

The method of claim 4, wherein a silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern to form the silicide blocking film on the gate electrode, the source region, and the drain region.

### Claim 6

A method of manufacturing a semiconductor device, the method comprising:
forming an active region defining an isolation region, a source region, and a drain region in a substrate;
forming a gate electrode disposed between the source region and the drain region and overlapping the active region; and
forming a gate silicide region and a silicide blocking region disposed on the gate electrode,
wherein the silicide blocking region comprises a body region and a plurality of protruding regions extended from the body region, and
wherein a horizontal width of the body region is greater than a horizontal width of each protruding region.

### Claim 7 (depends on 6)

The method of claim 6, wherein the plurality of protruding regions comprises:
a first protruding silicide blocking region disposed in the gate electrode and a portion of the source region; and
a second protruding silicide blocking region disposed in the gate electrode and a portion of the drain region.

### Claim 8 (depends on 7)

The method of claim 7, wherein the plurality of protruding regions further comprises a third protruding silicide blocking region protruded towards the drain region, and
wherein the silicide blocking region is disposed in contact with the second protruding silicide blocking region.

### Claim 9 (depends on 6)

The method of claim 6, wherein the body region is disposed to overlap the gate electrode, a portion of the source region, and a portion of the drain region.

### Claim 10 (depends on 6)

The method of claim 6, wherein the body region is disposed to overlap a portion of the gate electrode and the drain region.

### Claim 11 (depends on 10)

The method of claim 10, wherein an active mask pattern is configured to form the source region and the drain region in the substrate.

### Claim 12 (depends on 11)

The method of claim 11, wherein a gate electrode mask pattern is disposed to overlap the active mask pattern and is configured to form the gate electrode.

### Claim 13 (depends on 12)

The method of claim 12, wherein a silicide blocking mask pattern comprises a body region and protruding regions extended from the body region, and is disposed to overlap the gate electrode mask pattern and the active mask pattern to form the silicide blocking region in the gate electrode, the source region and the drain region.

### Claim 14 (depends on 13)

The method of claim 13, wherein the silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.