# US 2021/0242018 A1 · Semiconductor structure with an epitaxial layer

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- Number: US 2021/0242018 A1
- Document ID: US20210242018A1
- Status: Published application
- Kind: A1
- Application number: 17/218,112
- Filed: 2021-03-30
- Published: 2021-08-05
- Earliest claimed: 2018-12-12
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Hsiao-Pang Chou; Hon-Huei Liu; Ming-Chang Lu; Chin-Fu Lin; Yu-Cheng Tung
- Web page: https://patentgrep.com/patent/US20210242018A1

## CPC

- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D 62/40: Crystalline structures
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10H 20/01335: {the light-emitting regions comprising nitride materials}
- H10H 20/815: having stress relaxation structures, e.g. buffer layers
- H10H 20/817: characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/276: {Lateral overgrowth}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2925: {Surface structures}
- H10P 14/2926: {Crystal orientations}
- H10P 14/3216: {Nitrides}
- H10P 14/3416: {Nitrides}
- H10P 50/642: {Chemical etching}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

## Claims

### Claim 1

A semiconductor structure with an epitaxial layer, comprising:
a substrate;
a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns;
multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate;
a buffer layer on a surface of each of said multiple recesses; and
an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

### Claim 2 (depends on 1)

The semiconductor structure with an epitaxial layer of claim 1, further comprising multiple second voids formed between said above-surface portion of said epitaxial layer and said blocking layer.

### Claim 3 (depends on 2)

The semiconductor structure with an epitaxial layer of claim 2, wherein each of said second voids is formed respectively between two said recesses.

### Claim 4 (depends on 1)

The semiconductor structure with an epitaxial layer of claim 1, wherein said epitaxial layer further comprises multiple middle portions in said blocking layer, and each of said multiple middle portions connects said above-surface portion and one of said buried portions.

### Claim 5 (depends on 1)

The semiconductor structure with an epitaxial layer of claim 1, wherein a material of said buffer layer is aluminum nitride or aluminum gallium nitride (AlxGayN).

### Claim 6 (depends on 1)

The semiconductor structure with an epitaxial layer of claim 1, wherein said recess extends along <111> crystal faces of said substrate.

### Claim 7 (depends on 1)

The semiconductor structure with an epitaxial layer of claim 1, wherein said recess has a horizontal bottom surface.

### Claim 8 (depends on 1)

The semiconductor structure with an epitaxial layer of claim 1, wherein said substrate is a silicon substrate with <100> crystal faces.

### Claim 9 (depends on 1)

The semiconductor structure with an epitaxial layer of claim 1, wherein a material of said epitaxial layer is gallium nitride or aluminum gallium nitride (AlxGayN).