# US 2021/0242011 A1 · Method of forming structures including a vanadium or indium layer

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- Number: US 2021/0242011 A1
- Document ID: US20210242011A1
- Status: Published application
- Kind: A1
- Application number: 17/162,279
- Filed: 2021-01-29
- Published: 2021-08-05
- Earliest claimed: 2020-02-03
- Assignees: ASM IP Holding B.V.
- Applicants: ASM IP Holding B.V.
- Inventors: Eric James Shero; Michael Eugene Givens; Qi Xie; Charles Dezelah; Giuseppe Alessio Verni
- Web page: https://patentgrep.com/patent/US20210242011A1

## CPC

- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69397: {the material containing two or more metal elements}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 14/6939: {characterised by the metal}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods and systems for depositing vanadium and/or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and/or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and/or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and/or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

## Claims

### Claim 1

A method of forming a structure, the method comprising the steps of:
providing a substrate within a reaction chamber of a reactor; and
using a cyclical deposition process, depositing a layer comprising one or more of vanadium and indium onto a surface of the substrate,
wherein the cyclical deposition process comprises:
providing one or more of a vanadium precursor and an indium precursor to the reaction chamber; and
providing one or more of an oxygen reactant, a nitrogen reactant, a sulfur reactant, and a carbon reactant to the reaction chamber.

### Claim 2 (depends on 1)

The method of claim 1, wherein the vanadium precursor comprises one or more of a vanadium halide, a vanadium oxyhalide, a vanadium organometallic compound, and a vanadium metal organic compound.

### Claim 3 (depends on 1)

The method of claim 1, wherein the indium precursor comprises one or more of an indium alkyl compound, an indium cyclopentadienyl compound, an indium beta-diketonate compound, and an indium acetate compound.

### Claim 4 (depends on 1)

The method of claim 1, wherein the structure comprises a threshold voltage tuning layer comprising the layer comprising one or more of vanadium and indium.

### Claim 5 (depends on 1)

The method of claim 1, wherein the structure comprises a p-dipole shifter layer comprising the layer comprising one or more of vanadium and indium.

### Claim 6 (depends on 1)

The method of claim 1, wherein the structure comprises a gate all around structure.

### Claim 7 (depends on 6)

The method of claim 6, wherein the gate all around structure includes a high-k dielectric layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the cyclical deposition process comprises a cyclical chemical vapor deposition process.

### Claim 9 (depends on 1)

The method of claim 1, wherein the cyclical deposition process comprises a thermal process.

### Claim 10 (depends on 1)

The method of claim 1, wherein a thickness of the layer comprising one or more of vanadium and indium is between about 0.1 nm and about 5 nm.

### Claim 11 (depends on 1)

The method of claim 1, wherein the one or more of a vanadium precursor and an indium precursor comprises a halide and the step of providing one or more of an oxygen reactant, a nitrogen reactant, a sulfur reactant, and a carbon reactant to the reaction chamber comprises providing the oxygen reactant.

### Claim 12 (depends on 1)

The method of claim 1, wherein the vanadium precursor comprises a beta-diketonate compound.

### Claim 13 (depends on 1)

The method of claim 1, wherein the reactant comprises the oxygen reactant.

### Claim 14 (depends on 1)

The method of claim 1, wherein the structure comprises a barrier layer comprising the layer comprising one or more of vanadium and indium.

### Claim 15 (depends on 1)

The method of claim 1, wherein the structure comprises an etch stop layer comprising the layer comprising one or more of vanadium and indium.

### Claim 16 (depends on 1)

A structure comprising the layer comprising one or more of vanadium and indium formed according to the method of claim 1.

### Claim 17 (depends on 16)

The structure of claim 16, comprising a high-k dielectric layer overlying a semiconductor material.

### Claim 18 (depends on 17)

The structure of claim 17, wherein the layer comprising one or more of vanadium and indium is overlying and in contact with the high-k dielectric layer.

### Claim 19 (depends on 16)

The structure of claim 16, wherein a thickness of the layer comprising one or more of vanadium and indium is less than 5 nm.

### Claim 20 (depends on 16)

The structure of claim 16, wherein the layer comprising one or more of vanadium and indium comprises one or more of vanadium nitride and vanadium carbon nitride.

### Claim 21 (depends on 16)

A gate all around device comprising the structure of claim 16.

### Claim 22 (depends on 21)

The gate all around device of claim 21, wherein the layer comprising one or more of vanadium and indium comprises one or more of a vanadium oxide and an indium oxide.

### Claim 23 (depends on 16)

A metal oxide semiconductor (MOS) device comprising the structure of claim 16.

### Claim 24 (depends on 16)

A DRAM device comprising the structure of claim 16.

### Claim 25 (depends on 16)

A logic device comprising the structure of claim 16.

### Claim 26 (depends on 16)

A 3DNAND device comprising the structure of claim 16.

### Claim 27

A system comprising:
one or more reaction chambers;
a precursor gas source comprising one or more of a vanadium precursor and an indium precursor;
a reactant gas source comprising one or more of an oxygen reactant, a nitrogen reactant, a sulfur reactant, and a carbon reactant;
an exhaust source; and
a controller,
wherein the controller is configured to control gas flow into at least one of the one or more reaction chambers to form a layer comprising one or more of vanadium and indium overlying a surface of a substrate using a cyclical deposition process.