# US 2021/0241845 A1 · Determining read voltages for memory systems with machine learning

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- Number: US 2021/0241845 A1
- Document ID: US20210241845A1
- Status: Published application
- Kind: A1
- Application number: 17/073,800
- Filed: 2020-10-19
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Yung-Chun Li; Yu-Ming Huang; Chih-Huai Shih
- Web page: https://patentgrep.com/patent/US20210241845A1

## CPC

- G11C 29/42: using error correcting codes [ECC] or parity check
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06N 3/0442: characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/09: Supervised learning
- G06N 20/00: Machine learning
- G06N 20/10: using kernel methods, e.g. support vector machines [SVM]
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G06N 3/044: Recurrent networks, e.g. Hopfield networks
- G06N 3/045: Combinations of networks
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems with machine learning (ML) are provided. In one aspect, a memory system includes a memory and a memory controller configured to: obtain a first reading output of memory data using a first read voltage corresponding to a first set of parameters associated with the memory data; if the first reading output fails to pass an Error Correction Code (ECC) test, obtain a second reading output of the memory data using a second read voltage corresponding to a second set of parameters associated with the memory data and including the first set of parameters, the second read voltage being generated using at least one ML algorithm based on the second set of parameters; and if the second reading output passes the ECC test, output the second reading output as a target reading output of the memory data.

## Claims

### Claim 1

A memory system comprising:
a memory; and
a memory controller coupled to the memory and configured to:
obtain a first reading output of target memory data in the memory by using a first read voltage corresponding to a first set of parameters associated with the target memory data;
in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, obtain a second reading output of the target memory data by using a second read voltage corresponding to a second set of parameters associated with the target memory data, the second read voltage being generated using at least one machine learning (ML) algorithm based on the second set of parameters, the second set of parameters comprising the first set of parameters; and
in response to determining that the second reading output passes the ECC test, output the second reading output as a target reading output of the target memory data.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the memory controller is configured to generate the first read voltage using stored read voltage data based on the first set of parameters.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein the stored read voltage data is generated based on supervised ML training using a plurality of inputs associated with the memory and corresponding optimal read voltages, each of the optimal read voltages corresponding to a minimum failed bit count of a reading output for a respective page in the memory with a respective input of the inputs, each of the inputs comprising respective values of a plurality of parameters, the plurality of parameters comprising the first set of parameters.

### Claim 4 (depends on 3)

The memory system of claim 3, wherein each of the plurality of parameters has a respective influence level on a memory cell characteristic of the memory, and value intervals of the plurality of parameters in the inputs are determined based on the respective influence levels of the plurality of parameters.

### Claim 5 (depends on 3)

The memory system of claim 3, wherein the stored read voltage data comprises a transfer function generated based on the supervised ML training, the transfer function representing a relationship between an input of the plurality of parameters and an optimal read voltage.

### Claim 6 (depends on 2)

The memory system of claim 2, wherein the memory controller is configured to update the stored read voltage data with the second read voltage in response to determining that the second reading output passes the ECC test.

### Claim 7 (depends on 6)

The memory system of claim 6, wherein the memory controller is configured to:
update the stored read voltage data in response to determining that threshold voltages of states of memory cells in the target memory data are within corresponding predetermined ranges.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein the memory controller is configured to:
in response to determining that the second reading output fails to pass the ECC test, adjust the second set of parameters and generate a new second read voltage using the at least one ML algorithm based on the adjusted second set of parameters.

### Claim 9 (depends on 1)

The memory system of claim 1, wherein the memory controller is configured to:
determine whether the first reading output passes the ECC test by determining whether a failed bit count (FBC) of the first reading output is beyond a first predetermined threshold.

### Claim 10 (depends on 9)

The memory system of claim 9, wherein the memory controller is configured to:
in response to determining that the failed bit count of the first reading output is no more than the first predetermined threshold, determine whether the failed bit count of the first reading output is beyond a second predetermined threshold that is smaller than the first predetermined threshold.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein the memory controller is configured to:
in response to determining that the failed bit count of the first reading output is no more than the second predetermined threshold, output the first reading output as the target reading output of the target memory data.

### Claim 12 (depends on 10)

The memory system of claim 10, wherein the memory controller is configured to:
in response to determining that the failed bit count of the first reading output is beyond the second predetermined threshold and no more than the first predetermined threshold, generate a third read voltage using the at least one ML algorithm.

### Claim 13 (depends on 12)

The memory system of claim 12, wherein the memory controller is configured to:
update the stored read voltage data with the third read voltage.

### Claim 14 (depends on 1)

The memory system of claim 1, wherein the first set of parameters comprises at least one of address information, a number of P/E cycles, a reading temperature, a read disturbance level, or a retention time.

### Claim 15 (depends on 1)

The memory system of claim 1, wherein the second set of parameters comprises at least one of a failed bit count in the first reading output, a number of “1” values obtained for each read voltage, a number change of “1” values between a previous read voltage and a current read voltage, a read time, a syndrome of low-density parity-check (LDPC) code, or a number of iteration of LDPC code.

### Claim 16 (depends on 1)

The memory system of claim 1, wherein the at least one ML algorithm comprises at least one of a linear regression, a support vector regression, or a deep learning algorithm including a convolutional neural network (CNN) algorithm or a Recurrent Neural Network (RNN) algorithm.

### Claim 17

A memory system comprising:
a memory; and
a memory controller coupled to the memory and configured to:
determine a first read voltage using stored read voltage data based on a first set of parameters associated with memory data to be read from the memory;
obtain a first reading output by reading the memory data using the first read voltage;
determine whether the first reading output passes an Error Correction Code (ECC) test;
in response to determining that the first reading output fails to pass the ECC test, generate a second read voltage using at least one machine learning (ML) algorithm based on a second set of parameters associated with the memory data, the second set of parameters comprising the first set of parameters and at least one additional parameter;
obtain a second reading output by reading the memory data using the second read voltage;
determine whether the second reading output passes the ECC test; and
in response to determining that the second reading output passes the ECC test, output the second reading output as the memory data read from the memory.

### Claim 18 (depends on 17)

The memory system of claim 17, wherein the memory controller is configured to:
in response to determining that the second reading output passes the ECC test, update the stored read voltage data with the second read voltage.

### Claim 19

A memory controller coupled to a memory, the memory controller comprising:
at least one processor;
an Error Correction Code (ECC) circuit;
a machine learning (ML) circuit; and
at least non-transitory medium storing instructions executable by the processor,
wherein the memory controller is configured to:
determine, by the ML circuit, a first read voltage using stored read voltage data based on a first set of parameters associated with memory data to be read from the memory;
obtain, by the processor, a first reading output by reading the memory data using the first read voltage;
determine, by the ECC circuit, whether the first reading output passes an ECC test;
in response to determining that the first reading output does not pass the ECC test, generate, by the ML circuit, a second read voltage using at least one machine learning (ML) algorithm based on a second set of parameters associated with the memory data, the second set of parameters comprising the first set of parameters and at least one additional parameter;
obtain, by the processor, a second reading output by reading the memory data using the second read voltage;
determine, by the ECC circuit, whether the second reading output passes the ECC test; and
in response to determining that the second reading output passes the ECC test, output, by the processor, the second reading output as the memory data read from the memory.

### Claim 20 (depends on 19)

The memory controller of claim 19, wherein the stored read voltage data is stored in the memory, and
wherein the memory controller comprises a memory interface, and the ML circuit is configured to communicate with the memory through the memory interface.