# US 2021/0241843 A1 · Apparatus and method for verifying reliability of data read from memory device through clock modulation, and memory system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241843 A1 - Document ID: US20210241843A1 - Status: Published application - Kind: A1 - Application number: 16/868,116 - Filed: 2020-05-06 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Hyun Sub KIM; Ie Ryung PARK - Web page: https://patentgrep.com/patent/US20210241843A1 ## CPC - G06F 1/08: Clock generators with changeable or programmable clock frequency - G11C 29/38: Response verification devices - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - G11C 29/12015: {comprising clock generation or timing circuitry} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 7/1066: {Output synchronization} - G11C 29/42: using error correcting codes [ECC] or parity check - G11C 2207/2254: Calibration - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system including: a memory device looping back a first clock to generate a second clock and outputting read data that are read from a memory cell region of the memory device in synchronization with the second clock; and a memory controller generating the first clock that includes a plurality of modulation sections by performing a modulation operation on a source clock according to a specific scheme, outputting the first clock to the memory device, and receiving the read data in response to the second clock. The read data includes a plurality of section data corresponding to the plurality of modulation sections included in the second clock, respectively, and the memory controller verifies reliability of each of the plurality of section data included in the read data by performing a demodulation operation on the second clock according to the specific scheme. ## Claims ### Claim 1 A memory system, comprising: a memory device including a memory cell region for storing data, the memory device looping back a first clock to generate a second clock and outputting read data that are read from the memory cell region in synchronization with the second clock; and a memory controller generating the first clock that includes a plurality of modulation sections by performing a modulation operation on a source clock according to a specific scheme, outputting the first clock to the memory device, and receiving the read data in response to the second clock, wherein the read data includes a plurality of section data corresponding to the plurality of modulation sections included in the second clock, respectively, and the memory controller verifies reliability of each of the plurality of section data included in the read data by performing a demodulation operation on the second clock according to the specific scheme. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the modulation operation according to the specific scheme includes a frequency modulation operation using a plurality of frequencies, and wherein each of the plurality of modulation sections included in the first clock is detected based on a frequency difference. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the modulation operation according to the specific scheme includes a phase modulation operation using a plurality of phases, and wherein each of the plurality of modulation sections included in the first clock is detected based on a phase difference. ### Claim 4 (depends on 1) The memory system of claim 1, wherein the memory controller detects the plurality of modulation sections included in the second clock through the demodulation operation, and verifies whether one or more abnormal section data exist among the plurality of section data. ### Claim 5 (depends on 4) The memory system of claim 4, wherein when the abnormal section data exist among the plurality of section data, the memory controller requests the memory device to selectively re-read and output the abnormal section data from the memory cell region. ### Claim 6 (depends on 1) The memory system of claim 1, wherein the memory controller includes: a clock generator generating the source clock; a modulation circuit generating the first clock by performing the modulation operation on the source clock; an input circuit receiving the read data in response to the second clock; and a verification circuit verifying the reliability of the read data inputted through the input circuit by performing the demodulation operation on the second clock. ### Claim 7 A memory system, comprising: a memory device including a memory cell region for storing data, the memory device generating a modulation clock by performing a modulation operation on an externally inputted source clock according to a specific scheme, the modulation clock including a plurality of modulation sections, and outputting the modulation clock and read data that are read from the memory cell region in synchronization with the modulation clock; and a memory controller generating the source clock, outputting the source clock to the memory device, and receiving the read data in response to the modulation clock, wherein the read data includes a plurality of section data corresponding to the plurality of modulation sections included in the modulation clock, respectively, and the memory controller verifies reliability of each of the plurality of section data included in the read data by performing a demodulation operation on the modulation signal according to the specific scheme. ### Claim 8 (depends on 7) The memory system of claim 7, wherein the modulation operation according to the specific scheme includes a frequency modulation operation using a plurality of frequencies, and wherein each of the plurality of modulation sections included in the modulation clock is detected based on a frequency difference. ### Claim 9 (depends on 7) The memory system of claim 7, wherein the modulation operation according to the specific scheme includes a phase modulation operation using a plurality of phases, and wherein each of the plurality of modulation sections included in the modulation clock is detected based on a phase difference. ### Claim 10 (depends on 7) The memory system of claim 7, wherein the memory controller detects the plurality of modulation sections included in the modulation clock through the demodulation operation, and verifies whether one or more abnormal section data exist among the plurality of section data. ### Claim 11 (depends on 10) The memory system of claim 10, wherein when the abnormal section data exist among the plurality of section data, the memory controller requests the memory device to selectively re-read and output the abnormal section data from the memory cell region. ### Claim 12 (depends on 7) The memory system of claim 7, wherein the memory device further includes: a modulation circuit generating the modulation clock by performing the modulation operation on the source clock; and an output circuit outputting the read data read from the memory cell region in synchronization with the modulation clock. ### Claim 13 (depends on 12) The memory system of claim 12, wherein the memory controller includes: a clock generator generating the source clock; an input circuit receiving the read data in response to the modulation clock; and a verification circuit verifying the reliability of the read data inputted through the input circuit by performing the demodulation operation on the modulation clock. ### Claim 14 A method for operating a memory system including a memory device having a memory cell region for storing data, the method comprising: generating a modulation clock by performing a modulation operation on a source clock according to a specific scheme, the modulation clock including a plurality of modulation sections; outputting read data that are read from the memory cell region in synchronization with the modulation clock from the memory device, the read data including a plurality of section data corresponding to the plurality of modulation sections included in the modulation clock, respectively; and verifying reliability of each of the plurality of section data included in the read data by performing a demodulation operation on the modulation signal according to the specific scheme. ### Claim 15 (depends on 14) The method of claim 14, wherein the modulation operation according to the specific scheme includes a frequency modulation operation using a plurality of frequencies, and wherein each of the plurality of modulation sections included in the modulation clock is detected based on a frequency difference. ### Claim 16 (depends on 14) The method of claim 14, wherein the modulation operation according to the specific scheme includes a phase modulation operation using a plurality of phases, and wherein each of the plurality of modulation sections included in the modulation clock is detected based on a phase difference. ### Claim 17 (depends on 14) The method of claim 14, wherein the verifying of the reliability of the read data comprises: detecting the plurality of modulation sections included in the modulation clock through the demodulation operation; and verifying whether one or more abnormal section data exist among the plurality of section data. ### Claim 18 (depends on 17) The method of claim 17, further comprising when the abnormal section data exist among the plurality of section data in the verifying of the reliability of the read data, selectively re-reading the abnormal section data from the memory cell region and outputting the re-read abnormal section data from the memory device. ### Claim 19 (depends on 14) The method of claim 14, further comprising after generating the modulation clock outside the memory device, transferring the generated modulation clock to the memory device, wherein the memory device loops back the transferred modulation clock and outputs the read data that are read from the memory cell region in synchronization with the modulation clock from the memory device. ### Claim 20 (depends on 14) The method of claim 14, further comprising: generating the source clock outside the memory device; and transferring the source clock to the memory device, wherein the memory device generates the modulation clock based on the transferred source clock, and outputs the read data that are read from the memory cell region in synchronization with the modulation clock from the memory device.