# US 2021/0241839 A1 · Flash memory cell and associated high voltage row decoder

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- Number: US 2021/0241839 A1
- Document ID: US20210241839A1
- Status: Published application
- Kind: A1
- Application number: 17/239,397
- Filed: 2021-04-23
- Published: 2021-08-05
- Earliest claimed: 2016-05-18
- Assignees: Silicon Storage Technology, Inc.
- Applicants: Silicon Storage Technology, Inc.
- Inventors: Hieu Van Tran; Anh Ly; Thuan Vu
- Web page: https://patentgrep.com/patent/US20210241839A1

## CPC

- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 16/0425: {comprising cells containing a merged floating gate and select transistor}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 16/30: Power supply circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

## Claims

### Claim 1

A non-volatile memory device comprising:
an array of flash memory cells organized in rows and columns, each flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, and a source line terminal;
a high voltage circuit for generating a high voltage; and
a high voltage row decoder comprising an erase gate decoder and a source line decoder, wherein the high voltage row decoder selects one or more rows in response to select signals and wherein the erase gate decoder applies the high voltage to erase gate terminals of the one or more rows or the source line decoder applies the high voltage to source line terminals of the one or more rows;
wherein the erase gate decoder comprises transistors only of a PMOS type and the source line decoder comprises transistors only of a PMOS type.

### Claim 2 (depends on 1)

The non-volatile memory device of claim 1, wherein the erase gate decoder applies the high voltage to erase gate terminals of the one or more rows during an erase operation.

### Claim 3 (depends on 1)

The non-volatile memory device of claim 1, wherein the source line decoder applies the high voltage to source line terminals of the one or more rows during a program operation.

### Claim 4 (depends on 1)

The non-volatile memory device of claim 1, wherein the high voltage circuit comprises a high voltage level shifter.

### Claim 5 (depends on 4)

The non-volatile memory device of claim 4, wherein the high voltage circuit further comprises a current limiter.

### Claim 6 (depends on 1)

The non-volatile memory device of claim 1, wherein the high voltage circuit further comprises a current limiter.

### Claim 7

A method of operating a non-volatile memory device comprising an array of flash memory cells organized in rows and columns, each flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, and a source line terminal, the method comprising:
generating a high voltage;
selecting one or more rows in response to select signals; and
performing one of:
applying, by an erase gate decoder, the high voltage to erase gate terminals of the one or more rows; and
applying, by a source line decoder, the high voltage to source line terminals of the one or more rows;
wherein the erase gate decoder comprises transistors only of a PMOS type and the source line decoder comprises transistors only of a PMOS type.

### Claim 8 (depends on 7)

The method of claim 7, wherein the step of applying, by an erase gate decoder, the high voltage to erase gate terminals of the one or more rows occurs during an erase operation.

### Claim 9 (depends on 7)

The method of claim 7, wherein the step of applying, by a source line decoder, the high voltage to source line terminals of the one or more rows occurs during a program operation.

### Claim 10 (depends on 7)

The method of claim 7, wherein the generating step is performed by a high voltage circuit.

### Claim 11 (depends on 10)

The method of claim 10, wherein the high voltage circuit comprises a high voltage level shifter.

### Claim 12 (depends on 11)

The method of claim 11, wherein the high voltage circuit further comprises a current limiter.

### Claim 13 (depends on 10)

The method of claim 10, wherein the high voltage circuit further comprises a current limiter.