# US 2021/0241837 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241837 A1 - Document ID: US20210241837A1 - Status: Published application - Kind: A1 - Application number: 17/007,691 - Filed: 2020-08-31 - Published: 2021-08-05 - Earliest claimed: 2020-02-05 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hiroki DATE - Web page: https://patentgrep.com/patent/US20210241837A1 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/32: Timing circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 80/00: Direct bonding of chips, wafers or substrates - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 90/00: Package configurations - H10W 90/20: Configurations of stacked chips - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/792: {between multiple chips} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor memory device comprises a bit line and source line, a first memory cell and first and second transistors connected therebetween, a second memory cell and third and fourth transistors connected therebetween, and first through fifth wirings connected to the first and the second memory cells and gate electrodes of the first to the fourth transistors. At a first timing of a read operation, voltages of the first through third wirings are larger than voltages of the fourth and fifth wirings. At a second timing, voltages of the second and third wirings are larger than voltages of the fourth and fifth wirings. At a third timing, voltages of the fourth and fifth wirings are larger than their voltages at the second timing. At a fourth timing, voltages of the second and third wirings are larger than a voltage of the fourth wiring. ## Claims ### Claim 1 A semiconductor memory device comprising: a bit line; a source line; a first memory cell, a first select transistor, and a second select transistor, the first select transistor being connected between the first memory cell and the bit line, and the second select transistor being connected between the first memory cell and the source line; a second memory cell, a third select transistor, and a fourth select transistor, the third select transistor being connected between the second memory cell and the bit line, and the fourth select transistor being connected between the second memory cell and the source line; a first wiring electrically connected to the first memory cell and the second memory cell; a second wiring connected to agate electrode of the first select transistor; a third wiring connected to a gate electrode of the second select transistor; a fourth wiring connected to agate electrode of the third select transistor; and a fifth wiring connected to a gate electrode of the fourth select transistor, at a first timing, of a read operation on the first memory cell, voltages of the first wiring, the second wiring, and the third wiring being larger than voltages of the fourth wiring and the fifth wiring, at a second timing later than the first timing, of the read operation on the first memory cell, a voltage of the first wiring being smaller than a voltage of the first wiring at the first timing, and voltages of the second wiring and the third wiring being larger than voltages of the fourth wiring and the fifth wiring, at a third timing later than the second timing, of the read operation on the first memory cell, voltages of the fourth wiring and the fifth wiring being larger than voltages of the fourth wiring and the fifth wiring at the second timing, and at a fourth timing later than the third timing, of the read operation on the first memory cell, a voltage of the first wiring being smaller than a voltage of the first wiring at the first timing, and voltages of the second wiring and the third wiring being larger than a voltage of the fourth wiring. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein a voltage of the first wiring at the third timing is smaller than a voltage of the first wiring at the second timing. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein a voltage of the first wiring at the fourth timing is smaller than a voltage of the first wiring at the second timing. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein a voltage of the first wiring at a fifth timing later than the second timing and earlier than the third timing is smaller than a voltage of the first wiring at the second timing, and is larger than a voltage of the first wiring at the fourth timing. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein at the fourth timing, a voltage of the fifth wiring is larger than a voltage of the fourth wiring. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein at a sixth timing later than the fourth timing, voltages of the first through fifth wirings are larger than voltages of the fourth wiring and the fifth wiring at the second timing. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, comprising: a third memory cell, a fifth select transistor, and a sixth select transistor, the fifth select transistor being connected between the third memory cell and the bit line, and the sixth select transistor being connected between the third memory cell and the source line; and a sixth wiring connected to a gate electrode of the fifth select transistor, wherein the first wiring is electrically connected to the third memory cell, the third wiring is connected to a gate electrode of the sixth select transistor, at the first timing, of the read operation on the first memory cell, a voltage of the sixth wiring is larger than voltages of the fourth wiring and the fifth wiring, at the second timing, of the read operation on the first memory cell, a voltage of the sixth wiring is smaller than voltages of the second wiring and the third wiring, and at the fourth timing, of the read operation on the first memory cell, a voltage of the sixth wiring is smaller than voltages of the second wiring and the third wiring. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein at the third timing, a voltage of the sixth wiring is smaller than voltages of the second wiring and the third wiring. ### Claim 9 (depends on 7) The semiconductor memory device according to claim 7, wherein at a sixth timing later than the fourth timing, voltages of the first through sixth wirings are larger than voltages of the fourth wiring and the fifth wiring at the second timing. ### Claim 10 (depends on 1) The semiconductor memory device according to claim 1, comprising: a fourth memory cell connected between the first select transistor and the second select transistor; a fifth memory cell connected between the third select transistor and the fourth select transistor; and a seventh wiring electrically connected to the fourth memory cell and the fifth memory cell, wherein at the first timing, a voltage of the seventh wiring is larger than voltages of the fourth wiring and the fifth wiring, at the second timing, a voltage of the seventh wiring is larger than voltages of the fourth wiring and the fifth wiring, at the third timing, a voltage of the seventh wiring is larger than a voltage of the fourth wiring at the first timing and the second timing, and at the fourth timing, a voltage of the seventh wiring is larger than a voltage of the fourth wiring. ### Claim 11 (depends on 1) The semiconductor memory device according to claim 1, wherein a voltage of the second wiring at the third timing is larger than a voltage of the second wiring at the fourth timing, and a voltage of the third wiring at the third timing is larger than a voltage of the third wiring at the fourth timing. ### Claim 12 (depends on 11) The semiconductor memory device according to claim 11, wherein a voltage of the fifth wiring at the third timing is larger than a voltage of the fifth wiring at the fourth timing. ### Claim 13 (depends on 10) The semiconductor memory device according to claim 10, wherein a voltage of the second wiring at the third timing is larger than a voltage of the second wiring at the fourth timing, a voltage of the third wiring at the third timing is larger than a voltage of the third wiring at the fourth timing, and a voltage of the seventh wiring at the third timing is larger than a voltage of the seventh wiring at the fourth timing. ### Claim 14 A semiconductor memory device comprising: a bit line; a source line; a first memory cell, a first select transistor, and a second select transistor, the first select transistor being connected between the first memory cell and the bit line, and the second select transistor being connected between the first memory cell and the source line; a second memory cell, a third select transistor, and a fourth select transistor, the third select transistor being connected between the second memory cell and the bit line, and the fourth select transistor being connected between the second memory cell and the source line; a first wiring electrically connected to the first memory cell and the second memory cell; a second wiring connected to a gate electrode of the first select transistor; a third wiring connected to a gate electrode of the second select transistor; a fourth wiring connected to a gate electrode of the third select transistor; and a fifth wiring connected to a gate electrode of the fourth select transistor, in a write sequence on the first memory cell, there being executed a program operation and a verify operation, at a first timing, of the verify operation, voltages of the first wiring, the second wiring, and the third wiring being larger than voltages of the fourth wiring and the fifth wiring, at a second timing later than the first timing, of the verify operation, a voltage of the first wiring being smaller than a voltage of the first wiring at the first timing, and voltages of the second wiring and the third wiring being larger than voltages of the fourth wiring and the fifth wiring, at a third timing later than the second timing, of the verify operation, voltages of the fourth wiring and the fifth wiring being larger than voltages of the fourth wiring and the fifth wiring at the second timing, and at a fourth timing later than the third timing, of the verify operation, a voltage of the first wiring being smaller than a voltage of the first wiring at the first timing, and voltages of the second wiring and the third wiring being larger than a voltage of the fourth wiring. ### Claim 15 (depends on 14) The semiconductor memory device according to claim 14, wherein a voltage of the first wiring at the third timing is smaller than a voltage of the first wiring at the second timing. ### Claim 16 (depends on 14) The semiconductor memory device according to claim 14, wherein a voltage of the first wiring at the fourth timing is smaller than a voltage of the first wiring at the second timing. ### Claim 17 (depends on 16) The semiconductor memory device according to claim 16, wherein a voltage of the first wiring at a fifth timing later than the second timing and earlier than the third timing is smaller than a voltage of the first wiring at the second timing, and is larger than a voltage of the first wiring at the fourth timing. ### Claim 18 (depends on 14) The semiconductor memory device according to claim 14, wherein at the fourth timing, a voltage of the fifth wiring is larger than a voltage of the fourth wiring. ### Claim 19 (depends on 14) The semiconductor memory device according to claim 14, wherein at a sixth timing later than the fourth timing, voltages of the first through fifth wirings are larger than voltages of the fourth wiring and the fifth wiring at the second timing.